Network flow based multi-way partitioning with area and pin constraints

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Network flow based multi-way partitioning with area and pin constraints

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 12 - 17

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Huiqun Liu	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 11, Downloads (12 Months): 24, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Honghua Yang , D. F. Wong, Efficient network flow based min-cut balanced partitioning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.50-55, November 06-10, 1994, San Jose, California, United States
	2	Jianmin Li , John Lillis , Chung-Kuan Cheng, Linear decomposition algorithm for VLSI design applications, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.223-228, November 05-09, 1995, San Jose, California, United States
	3	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral-based multi-way FPGA partitioning, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.133-139, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201331]
	4	Dennis J.-H. Huang , Andrew B. Kahng, Multi-way system partitioning into a single type or multiple types of FPGAs, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.140-145, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201332]
	5	Nan-Chi Chou , Lung-Tien Liu , Chung-Kuan Cheng , Wei-Jin Dai , Rodney Lindelof, Circuit partitioning for huge logic emulation systems, Proceedings of the 31st annual conference on Design automation, p.244-249, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196365]
	6	Roman Kužnar , Franc Brglez , Krzysztof Kozminski, Cost minimization of partitions into multiple devices, Proceedings of the 30th international conference on Design automation, p.315-320, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164910]
	7	Nam Sung Woo , Jaeseok Kim, An efficient method of partitioning circuits for multiple-FPGA implementation., Proceedings of the 30th international conference on Design automation, p.202-207, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164669]
	8	M. Shih , E. S. Kuh , R.-S. Tsay, Performance-driven system partitioning on multi-chip modules, Proceedings of the 29th ACM/IEEE conference on Design automation, p.53-56, June 08-12, 1992, Anaheim, California, United States
	9	J.R. Ford and D.R. Fulkerson, Flows in Networks, Princeton University Press, 1962.
	10	L. James Hwang and Abbas El Gamal, "Min-Cut Replication in Partitioned Networks", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol 14, No. 1, pp96-106, Jan. 1995.
	11	L. A. Sanchis, Multiple-Way Network Partitioning, IEEE Transactions on Computers, v.38 n.1, p.62-81, January 1989 [doi>10.1109/12.8730]