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ABSTRACT

A trace driven methodology for logic synthesis and optimization is proposed. Given a logic description of a digital circuit C and an expected trace of input vectors T an implementation of C that optimizes a cost function under application of T is derived. This approach is effective in capturing and utilizing the correlations that exist between input signals on an application specific design. The idea is novel since it propose synthesis and optimization at the logic level where the goal is to optimize the average case rather than the worst case for a chosen cost metric. This paper focuses on the development of algorithms for trace driven optimization to minimize the switching power in multi-level networks. The average net power reduction (internal plus I/O power) obtained on a set of benchmark FSMs is 14%, while the average reduction in internal power is 25%. We also demonstrate that the I/O transition activity provides an upper bound on the power reduction that can be achieved by combinational logic synthesis.

REFERENCES

• 1: Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
• 2: Olivier Coudert, On solving covering problems, Proceedings of the 33rd annual conference on Design automation, p.197-202, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240555]
• 3: Olivier Coudert , Ramsey Haddad, Integrated resynthesis for low power, Proceedings of the 1996 international symposium on Low power electronics and design, p.169-174, August 12-14, 1996, Monterey, California, United States
• 4: Gary D. Hachtel , Mariano Hermida , Abelardo Pardo , Massimo Poncino , Fabio Somenzi, Re-encoding sequential circuits to reduce power dissipation, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.70-73, November 06-10, 1994, San Jose, California, United States
• 5: Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217537]
• 6: Sasan Iman , Massoud Pedram, Two-level logic minimization for low power, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.433-438, November 05-09, 1995, San Jose, California, United States
• 7: Radu Marculescu , Diana Marculescu , Massoud Pedram, Efficient power estimation for highly correlated input streams, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.628-634, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217601]
• 8: R. Murgai , R. K. Brayton , A. Sangiovanni-Vincentelli, Decomposition of logic functions for minimum transition activity, Proceedings of the 1995 European conference on Design and Test, p.404, March 06-09, 1995
• 9: Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
• 10: Farid N. Najm, Feedback, correlation, and delay concerns in the power estimation of VLSI circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.612-617, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217598]
• 11: J. Rajski and J. Vasudevamurthy. The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Espression. IEEE Transactions on Computer-Aided Design, 11:778-793,1992.
• 12: K. Roy and S.C. Prasad. Circuit Activity Based Logic Synthesis for Low Power Reliable Operations. IEEE Transactions on VLSI Systems, 1:503-513,1993.
• 13: Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
• 14: Chi-Ying Tsui , Radu Marculescu , Diana Marculescu , Massoud Pedram, Improving the efficiency of power simulators by input vector compaction, Proceedings of the 33rd annual conference on Design automation, p.165-168, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240549]
• 15: Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Efficient estimation of dynamic power consumption under a real delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.224-228, November 07-11, 1993, Santa Clara, California, United States
• 16: Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Exact and approximate methods for calculating signal and transition probabilities in FSMs, Proceedings of the 31st annual conference on Design automation, p.18-23, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196255]
• 17: Albert Ren Rui Wang, Algorithms for multilevel logic optimization, University of California at Berkeley, Berkeley, CA, 1991

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Simulation

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Automatic synthesis

  J. Computer Applications

General Terms:
Algorithms, Design, Experimentation, Measurement, Performance, Theory

Keywords:
Logic Synthesis, Low Power