Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

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Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

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International Conference on Computer Aided Design archive
Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 260 - 265

Year of Publication: 1997

ISBN:0-8186-8200-0

Authors

Atsushi Takahashi	Dept. of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo 152, Japan
Kazunori Inoue	Hitachi ULSI Engineering, 3-1-1 Higashi-Koigakubo, Kokubunji, Tokyo 185, Japan
Yoji Kajitani	Hitachi ULSI Engineering, 3-1-1 Higashi-Koigakubo, Kokubunji, Tokyo 185, Japan

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

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IEEE Computer Society Washington, DC, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 22, Citation Count: 4

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ABSTRACT

It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and determines the locations and sizes of intermediate buffers simultaneously. The experimental results show that this method constructs clock-trees with moderate wire length compared with that of zero-skew clock-trees.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 4

	M. Saitoh , M. Azuma , A. Takahashi, Clustering based fast clock scheduling for light clock-tree, Proceedings of the conference on Design, automation and test in Europe, p.240-245, March 2001, Munich, Germany
	Masahiko Toyonaga , Keiichi Kurokawa , Takuya Yasui , Atsushi Takahashi, A practical clock tree synthesis for semi-synchronous circuits, Proceedings of the 2000 international symposium on Physical design, p.159-164, May 2000, San Diego, California, United States
	Xinjie Wei , Yici Cai , Xianlong Hong, Physical aware clock skew rescheduling, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Saif Ali Butt , Stefan Schmermbeck , Jurij Rosenthal , Alexander Pratsch , Eike Schmidt, System level clock tree synthesis for power optimization, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France