Application-driven synthesis of core-based systems

ABSTRACT

We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraining most-constrained heuristic to minimize the instruction cache misses for a given application, instruction cache size and organization. Based on this performance optimization technique, we constructed a strategy to search for a minimal-area processor core, and an instruction and data cache which satisfy the performance characteristics of a set of target applications. The synthesis platform integrates the existing modeling, profiling, and simulation tools with the developed system-level synthesis tools. The effectiveness of the approach is demonstrated on a variety of modern real-life multimedia and communication applications.

REFERENCES

• Bol94: I. Bolsens, K. Rompaey, H. De Man, "User requirements for designing complex systems on silicon", VLSI Signal Processing VII, pp. 63-72, 1994.
• Chi96: Massimiliano Chiodo , Daniel Engels , Paolo Giusto , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Kei Suzuki , Alberto Sangiovanni-Vincentelli, A case study in computer-aided co-design of embedded controllers, Design Automation for Embedded Systems, v.1 n.1-2, p.51-67, Jan. 1996 [doi>10.1007/BF00134683]
• Cme94: Bob Cmelik , David Keppel, Shade: a fast instruction-set simulator for execution profiling, ACM SIGMETRICS Performance Evaluation Review, v.22 n.1, p.128-137, May 1994
• CPU: http://infopad.eecs.berkeley.edu/CIC/
• Fly96: Michael J. Flynn, Computer Architecture: Pipelined and Parallel Processor Design, Jones and Bartlett Publishers, Inc., 1995
• Gaj94: D.D. Gajski, et al. "A System-Design Methodology: Executable Specification Refinement", Euro-DAC, pp. 458-463, 1994.
• Gar79: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• Gup93: Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
• Hen95: Jörg Henkel , Rolf Ernst, A path-based technique for estimating hardware runtime in HW/SW-cosynthesis, Proceedings of the 8th international symposium on System synthesis, p.116-121, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224527]
• Hill88: Mark D. Hill, A Case for Direct-Mapped Caches, Computer, v.21 n.12, p.25-40, December 1988 [doi>10.1109/2.16187]
• Jou93: Norman P. Jouppi, Cache write policies and performance, ACM SIGARCH Computer Architecture News, v.21 n.2, p.191-201, May 1993
• Kir97: D. Kirovski, et al., "Synthesis of core-based application-specific systems", Technical Report, CSD, UCLA, 1997.
• Lee96: Tsing-Gen Lee , Wen-Jong Fang , Allen C.-H. Wu, The design and implementation of a cooperative design-view environment for interactive partitioning applications, Software—Practice & Experience, v.26 n.10, p.1141-1160, Oct. 1996 [doi>10.1002/(SICI)1097-024X(199610)26:10<1141::AID-SPE52>3.0.CO;2-K]
• Lie96: Clifford Liem , Pierre Paulin , Ahmed Jerraya, Address calculation for retargetable compilation and exploration of instruction-set architectures, Proceedings of the 33rd annual conference on Design automation, p.597-600, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240631]
• MPR96: Microprocessor Report, all isues, 1996.
• Pot95: Miodrag Potkonjak , Wayne Wolf, Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.446-451, November 05-09, 1995, San Jose, California, United States
• Sub96: P. A. Subrahmanyam , A. Sharma, Issues in developing real-time multimedia applications for a multiprocessor system, Proceedings of the 4th International Workshop on Parallel and Distributed Real-Time Systems, p.147, April 15-16, 1996

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Heuristic methods

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies
      B.7.2 Design Aids
          Subjects: Simulation

  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

General Terms:
Algorithms, Design, Measurement, Performance, Theory

Keywords:
application-specific system-level synthesis, system modeling and performance evaluation, cache line coloring