|
ABSTRACT
This paper describes PRIMA, an algorithm for generating provably passive reduced order N-port models for RLC interconnect circuits. It is demonstrated that, in addition to requiring macromodel stability, macromodel passivity is needed to guarantee the overall circuit stability once the active and passive driver/load models are connected. PRIMA extends the block Arnoldi technique to include guaranteed passivity. Moreover, it is empirically observed that the accuracy is superior to existing block Arnoldi methods. While the same passivity extension is not possible for MPVL, we observed comparable accuracy in the frequency domain for all examples considered. Additionally a path tracing algorithm is used to calculate the reduced order macromodel with the utmost efficiency for generalized RLC interconnects.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis", IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 352-366, Apr. 1990.
|
| |
2
|
E Feldmann and R. W. Freund, "Efficient linear circuit analysis by Pad6 approximation via the Lanczos process", IEEE Trans. on CAD, vol. CAD-14, pp. 639-649, May 1995
|
| |
3
|
Kevin J. Kerns , Ivan L. Wemple , Andrew T. Yang, Stable and efficient reduction of substrate model networks using congruence transforms, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.207-214, November 05-09, 1995, San Jose, California, United States
|
 |
4
|
L. Miguel Silveira , Mattan Kamon , Jacob White, Efficient reduced-order modeling of frequency-dependent coupling inductances associated with 3-D interconnect structures, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.376-380, June 12-16, 1995, San Francisco, California, United States
[doi> 10.1145/217474.217558]
|
 |
5
|
|
| |
6
|
D. L. Boley, "Krylov space methods on state-space control models", Circuits Syst. Signal Process. vol.13, no.6, pp. 733-758, 1994
|
| |
7
|
S. Y. Kim, N. Gopal and L. T. Pillage, "Time-Domain Macromodels for VLSI Interconnect Analysis", IEEE Trans. on CAD, vol 13, No. 10, pp. 1257-1270, Oct. 1994
|
| |
8
|
L. Miguel Silveira , Mattan Kamon , Ibrahim Elfadel , Jacob White, A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.288-294, November 10-14, 1996, San Jose, California, United States
|
 |
9
|
|
 |
10
|
|
| |
11
|
B. D. Anderson and S. Vongpanitlerd, Network analysis and synthesis. Prentice-Hall, Inc., 1973
|
| |
12
|
R. A. Rohrer and H. Nosrati, "Passivity considerations in stability studies of numerical integration algorithms", IEEE Trans. on Circuits and Systems, vol. CAS-28, no. 9, pp. 857-866, Sep. 1981
|
| |
13
|
C. L. Ratzlaff and L. T. Pillage, "RICE: Rapid interconnect circuit evaluation using AWE", IEEE Trans. CAD, vol. 13, no. 6, pp. 763- 776, Jun. 1994
|
| |
14
|
V. Raghavan , J. E. Bracken , R. A. Rohrer, AWESpice: a general tool for the accurate and efficient simulation of interconnect problems, Proceedings of the 29th ACM/IEEE conference on Design automation, p.87-92, June 08-12, 1992, Anaheim, California, United States
|
| |
15
|
G. H. Golub and C. F. Van Loan, Matrix Computations. John Hopkins Univ. Press, 2nd ed., 1989
|
| |
16
|
E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks. Holden-Day Inc., 1967
|
| |
17
|
L. W. Nagel, "SPICE2, a computer program to simulate semiconductor circuits", Technical Report ERL-M520, UC-Berkeley, May 1975
|
| |
18
|
T. L. Quarles, "The SPICE3 implementation guide", Tech. Rep. Memo ERL-M89/44, U. of California, Berkeley, 1989
|
| |
19
|
|
| |
20
|
X. Huang, "Pad6 approximation of linear(ized) circuit responses", Ph.D. Thesis, Carnegie Mellon Univ., Nov. 1990
|
CITED BY 90
|
|
|
|
|
|
|
|
M. M. Gourary , S. G. Rusakov , S. L. Ulyanov , M. M. Zharov , B. J. Mulvaney, An optimum fitting algorithm for generation of reduced-order models, Proceedings of the 2001 conference on Asia South Pacific design automation, p.209-213, January 2001, Yokohama, Japan
|
|
|
|
|
|
Janet M. Wang , Ernest S. Kuh , Qingjian Yu, The Chebyshev expansion based passive model for distributed interconnect networks, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.370-375, November 07-11, 1999, San Jose, California, United States
|
|
|
Luca Daniel , Chin Siong Ong , Sok Chay Low , Kwok Hong Lee , Jacob White, Geometrically parameterized interconnect performance models for interconnect synthesis, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
|
|
|
|
|
|
Andrew B. Kahng , Sudhakar Muddu , Egino Sarto, On switch factor based analysis of coupled RC interconnects, Proceedings of the 37th conference on Design automation, p.79-84, June 05-09, 2000, Los Angeles, California, United States
|
|
|
Qingjian Yu , Janet M. Wang , Ernest S. Kuh, Multipoint moment matching model for multiport distributed interconnect networks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.85-91, November 08-12, 1998, San Jose, California, United States
|
|
|
|
|
|
Tao Lin , Emrah Acar , Lawrence Pileggi, h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.19-25, November 08-12, 1998, San Jose, California, United States
|
|
|
|
|
|
H. Levy , W. Scott , D. MacMillen , Jacob White, A rank-one update method for efficient processing of interconnect parasitics in timing analysis, Proceedings of the 37th conference on Design automation, p.75-78, June 05-09, 2000, Los Angeles, California, United States
|
|
|
|
|
|
G. Van der Plas , M. Badaroglu , G. Vandersteen , P. Dobrovolny , P. Wambacq , S. Donnay , G. Gielen , H. De Man, High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
|
|
|
|
|
|
Paul D. Gross , Ravishankar Arunachalam , Karthik Rajagopal , Lawrence T. Pileggi, Determination of worst-case aggressor alignment for delay calculation, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.212-219, November 08-12, 1998, San Jose, California, United States
|
|
|
Nuno Marques , Mattan Kamon , Jacob White , L. Miguel Silveira, A mixed nodal-mesh formulation for efficient extraction and passive reduced-order modeling of 3D interconnects, Proceedings of the 35th annual conference on Design automation, p.297-302, June 15-19, 1998, San Francisco, California, United States
|
|
|
|
|
|
Jing-Rebecca Li , Frank Wang , Jacob K. White, An efficient Lyapunov equation-based approach for generating reduced-order models of interconnect, Proceedings of the 36th ACM/IEEE conference on Design automation, p.1-6, June 21-25, 1999, New Orleans, Louisiana, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States
|
|
|
|
|
|
|
|
|
M. Kamon , N. Marques , Y. Massoud , L. Silveira , J. White, Interconnect analysis: from 3-D structures to circuit models, Proceedings of the 36th ACM/IEEE conference on Design automation, p.910-914, June 21-25, 1999, New Orleans, Louisiana, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
N. Marques , M. Kamon , J. White , L. M. Silveira, An efficient algorithm for fast parasitic extraction and passive order reduction of 3D interconnect models, Proceedings of the conference on Design, automation and test in Europe, p.538-543, February 23-26, 1998, Le Palais des Congrés de Paris, France
|
|
|
Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States
|
|
|
|
|
|
|
|
|
|
|
|
Rafi Levy , David Blaauw , Gabi Braca , Aurobindo Dasgupta , Amir Grinshpon , Chanlee Oh , Boaz Orshav , Supamas Sirichotiyakul , Vladimir Zolotov, ClariNet: a noise analysis tool for deep submicron design, Proceedings of the 37th conference on Design automation, p.233-238, June 05-09, 2000, Los Angeles, California, United States
|
|
|
|
|
|
Xiaoning Qi , Goetz Leonhardt , Daniel Flees , Xiao-Dong Yang , Sangwoo Kim , Stephan Mueller , Hendrik Mau , Lawrence T. Pileggi, A fast simulation approach for inductive effects of VLSI interconnects, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
|
|
|
|
|
|
|
|
|
|
|
|
Supamas Sirichotiyakul , David Blaauw , Chanhee Oh , Rafi Levy , Vladimir Zolotov , Jingyan Zuo, Driver modeling and alignment for worst-case delay noise, Proceedings of the 38th conference on Design automation, p.720-725, June 2001, Las Vegas, Nevada, United States
|
|
|
Al Dunlop , Alper Demir , Peter Feldmann , Sharad Kapur , David Long , Robert Melville , Jaijeet Roychowdhury, Tools and methodology for RF IC design, Proceedings of the 35th annual conference on Design automation, p.414-420, June 15-19, 1998, San Francisco, California, United States
|
|
|
|
|
|
V. Zolotov , D. Blaauw , S. Sirichotiyakul , M. Becer , C. Oh , R. Panda , A. Grinshpon , R. Levy, Noise propagation and failure criteria for VLSI designs, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.587-594, November 10-14, 2002, San Jose, California
|
|
|
Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
|
|
|
|
|
|
Zhengyong Zhu , Khosro Rouz , Manjit Borah , Chung-Kuan Cheng , Ernest S. Kuh, Efficient transient simulation for transistor-level analysis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
|
|
|
|
|
|
Jingyu Xu , Xianlong Hong , Tong Jing , Ling Zhang , Jun Gu, A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.677-682, January 27-30, 2004, Yokohama, Japan
|
|
|
Yahong Cao , Yu-Min Lee , Tsung-Hao Chen , Charlie Chung-Ping Chen, HiPRIME:: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
|
|
|
|
|
|
|
|
|
|
|
|
Jingyu Xu , Xianlong Hong , Tong Jing , Yici Cai , Jun Gu, A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
|
|
|
Haitian Hu , David T. Blaauw , Vladimir Zolotov , Kaushik Gala , Min Zhao , Rajendran Panda , Sachin S. Sapatnekar, A precorrected-FFT method for simulating on-chip inductance, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.221-227, November 10-14, 2002, San Jose, California
|
|
|
|
|
|
|
|
|
|
|
|
Jingyu Xu , Xianlong Hong , Tong Jing , Ling Zhang , Jun Gu, A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design, Integration, the VLSI Journal, v.39 n.4, p.457-473, July 2006
|
|
|
|
|
|
|
|
|
|
|
|
Xuanzeng , Lihong Feng , Yangfeng Su , Wei Cai , Dian Zhou , Charles Chiang, Time domain model order reduction by wavelet collocation method, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S. Raja , F. Varadi , M. Becer , J. Geada, Transistor level gate modeling for accurate and fast timing, noise, and power analysis, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
C.1
PROCESSOR ARCHITECTURES
C.1.2
Multiple Data Stream Architectures (Multiprocessors)
Subjects:
Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)
Additional Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.1
Types and Design Styles
Subjects:
Memory technologies
C.
Computer Systems Organization
General Terms:
Algorithms,
Design,
Performance,
Reliability,
Theory
Keywords:
CAD,
MPVL,
PRIMA,
RLC interconnect circuits,
block Arnoldi technique,
circuit stability,
driver-load models,
frequency domain,
guaranteed passivity,
integrated circuit layout,
macromodel passivity,
macromodel stability,
passive reduced-order interconnect macromodeling algorithm,
path tracing algorithm,
reduced order N-port models,
simulation
|