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Generalized matching from theory to application
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Source International Conference on Computer Aided Design archive
Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 13 - 20  
Year of Publication: 1997
ISBN:0-8186-8200-0
Authors
Patrick Vuillod  Synopsys-Europe and Stanford University, Computer Systems Laboratory, Stanford, CA
Luca Benini  Stanford University, Computer Systems Laboratory, Stanford, CA
Giovanni De Micheli  Stanford University, Computer Systems Laboratory, Stanford, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 8,   Citation Count: 0
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ABSTRACT

We present a novel approach for post-mapping optimization. We exploit the concept of generalised matching, a technique that finds symbolically all possible matching assignments of library cells to a multi-output network specified by a Boolean relation. Several objectives are targeted: area minimization under delay constraints; power minimization under delay constraints; and unconstrained delay minimization. We describe the theory of generalized matching and the algorithmic optimization required for its efficient and robust implementation. A tool based on generalized matching has been implemented and tested on large examples of the MCNC'91 benchmark suite. We obtain sizable improvements in: speed (6% in average, up to 20.7%); area under speed constraints (13.7% an average, up to 29.5%); and power under speed constraints (22.3% in average, up to 38.1%).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
F. Somenzi et al., "Minimization of Boolean relations," in IS- CAS, pp. 738-473, 1989.
 
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R. Brayton et al., "Multilevel logic synthesis," IEEE Proceedings, vol. 78, pp. 264-300, 1990.
 
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H. Savoj et al., "Extracting local don't cares for network optimization," in ICCAD, pp. 514-517, 1991.
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K. Cheng et al., "Multi-level logic optimization by redundancy addition and removal," in Euro-DAC, pp. 373-377, 1993.
 
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Y. Watanabe et al., "Permissible functions for multioutput components in combinational logic optimization," IEEE TCAD ICAS, vol. 15, no. 7, pp. 734-744, 1996.
 
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F. Somenzi. The CUDD package User's guide. Version 1.0.5 1995.
 
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S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide Version 3.0," Tech. Rep. MCNC, 1991.
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Collaborative Colleagues:
Patrick Vuillod: colleagues
Luca Benini: colleagues
Giovanni De Micheli: colleagues