Hardware/software partitioning and pipelining

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Hardware/software partitioning and pipelining

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 713 - 716

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Smita Bakshi	Department of Electrical & Computer Engineering, University of California, Davis, CA
Daniel D. Gajski	Department of Information & Computer Science, University of California, Irvine, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 27, Citation Count: 7

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

For a given throughput constrained system-level specification,we present a design flow and an algorithm to select software(general purpose processors) and hardware components,and then partition and pipeline the specification amongstthe selected components.This is done so as to beat satisfythe throughput constraint at minimal hardware cost.Ourability to pipeline the design at several levels, enables us toattain high throughput designs, and also distinguishes ourwork from previously proposed hardware/software partitioning algorithms.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Daniel D. Gajski , Frank Vahid , Sanjiv Narayan , Jie Gong, Specification and design of embedded systems, Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
	2	Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964]
	3	Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
	4	Asawaree Prabhakar Kalavade , Edward A. Lee, System-level codesign of mixed hardware-software systems, 1995
	5	Jie Gong , Daniel D. Gajski , Sanjiv Narayan, Software estimation from executable specifications, Journal of Computer and Software Engineering, v.2 n.3, p.239-258, 1994
	6	R. Gupta and G. D. Micheli, "Partitioning of functional models of synchronous digital systems," in Proceedings of the IEEE International Conference on Computer Aided Design, pp. 216-219, 1990.
	7	F. Vahid , D. D. Gajski, Specification partitioning for system design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.219-224, June 08-12, 1992, Anaheim, California, United States
	8	D. Gajski, P. Grun, W. Pan, and S. Bakshi, "Design exploration for pipelined IDCT," Tech. Rep. 96-41, Dept. of Information and Computer Science, University of California, Irvine, 1996.
	9	A. B. Thordarson, "Comparison of manual and automatic behavioral synthesis on MPEG-algorithm," Master's thesis, University of California, Irvine, 1995.

CITED BY 7

	Karam S. Chatha , Ranga Vemuri, RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns, Proceedings of the 6th international workshop on Hardware/software codesign, p.139-143, March 15-18, 1998, Seattle, Washington, United States
	An algorithm for synthesis of large time-constrained heterogeneous adaptive systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.207-225, April 2001
	Smita Bakshi , Daniel D. Gajski, A scheduling and pipelining algorithm for hardware/software systems, Proceedings of the 10th international symposium on System synthesis, p.113-118, September 17-19, 1997, Antwerp, Belgium
	U. Nagaraj Shenoy , Prith Banerjee , Alok Choudhary, A system-level synthesis algorithm with guaranteed solution quality, Proceedings of the conference on Design, automation and test in Europe, p.417-425, March 27-30, 2000, Paris, France
	Daniel Ragan , Peter Sandborn , Paul Stoaks, A detailed cost model for concurrent use with hardware/software co-design, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Karam S. Chatha , Ranga Vemuri, A tool for partitioning and pipelined scheduling of hardware-software systems, Proceedings of the 11th international symposium on System synthesis, p.145-151, December 02-04, 1998, Hsinchu, Taiwan, China
	Francesco Poletti , Antonio Poggiali , Davide Bertozzi , Luca Benini , Pol Marchal , Mirko Loghi , Massimo Poncino, Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support, IEEE Transactions on Computers, v.56 n.5, p.606-621, May 2007