| COSYN: hardware-software co-synthesis of embedded systems |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 703 - 708
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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Bharat P. Dave
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Department of Electrical Engineering, Princeton University, Princeton, NJ
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Ganesh Lakshminarayana
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Department of Electrical Engineering, Princeton University, Princeton, NJ
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Niraj K. Jha
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Department of Electrical Engineering, Princeton University, Princeton, NJ
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Downloads (6 Weeks): 4, Downloads (12 Months): 51, Citation Count: 39
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 ABSTRACT
Hardware-software co-synthesis is the process ofpartitioning an embedded system specification into hardware andsoftware modules to meet performance, power and cost goals. Inthis paper, we present a co-synthesis algorithm which starts withperiodic task graphs with real-time constraints and produces a low-costheterogeneous distributed embedded system architecturemeeting the constraints. The algorithm has the following features:1) it allows the use of multiple types of processing elements (PEs)and inter-PE communication links, where the links can take variousforms (point-to-point, bus, local area network (LAN), etc.), 2) itsupports both concurrent and sequential modes of communicationand computation, 3) it allows both preemptive and non-preemptivescheduling, 4) it employs the concept of an association array totackle the problem of multi-rate systems (which are commonlyfound in multimedia applications), 5) it uses a scheduler based ondynamic deadline-based priority levels for accurate performanceestimation of a co-synthesis solution, 6) it uses a new taskclustering technique which takes the dynamic nature of the criticalpath, and the existence of multiple critical paths in the task graphinto account, and 7) if desired, it also optimizes the architecture forpower consumption (we are not aware of any other co-synthesisalgorithm that optimizes power). Application of the proposedalgorithm to examples from the literature and real-life telecomtransport systems shows its efficacy.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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R.K. Gupta, Hardware-Software Co-synthesis of Digital Systems, Ph.D. thesis, Dept. of EE, Stanford University, 1994.
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B.P. Dave, G. Lakshminarayana, and N. K. Jha, "COSYN: Hardware-software co-synthesis of embedded systems," Tech. Rep., CE-J96-003, Dept. of EE, Princeton University, Oct. 1996.
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V. Tiwari, S. Malik and A. Wolfe, "Compilation techniques for low energy: An overview," in Proc. Syrup. Low-Power Electronics, Oct. 1994.
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CITED BY 39
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Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
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X. Hu , G. W Greenwood , S. Ravichandran , G. Quan, A framework for user assisted design space exploration, Proceedings of the 36th ACM/IEEE conference on Design automation, p.414-419, June 21-25, 1999, New Orleans, Louisiana, United States
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Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
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Robert P. Dick , David L. Rhodes , Wayne Wolf, TGFF: task graphs for free, Proceedings of the 6th international workshop on Hardware/software codesign, p.97-101, March 15-18, 1998, Seattle, Washington, United States
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Yanbing Li , Tim Callahan , Ervan Darnell , Randolph Harr , Uday Kurkure , Jon Stockwood, Hardware-software co-design of embedded reconfigurable architectures, Proceedings of the 37th conference on Design automation, p.507-512, June 05-09, 2000, Los Angeles, California, United States
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Kanishka Lahiri , Anand Raghunathan , Ganesh Lakshminarayana , Sujit Dey, Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips, Proceedings of the 37th conference on Design automation, p.513-518, June 05-09, 2000, Los Angeles, California, United States
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Luc Bianco , Michel Auguin , Guy Gogniat , Alain Pegatoquet, A path analysis based partitioning for time constrained embedded systems, Proceedings of the 6th international workshop on Hardware/software codesign, p.85-89, March 15-18, 1998, Seattle, Washington, United States
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Marlene Wan , Hui Zhang , Varghese George , Martin Benes , Arthur Abnous , Vandana Prabhu , Jan Rabaey, Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System, Journal of VLSI Signal Processing Systems, v.28 n.1-2, p.47-61, May-June 2001
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