System-level synthesis of low-power hard real-time systems

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System-level synthesis of low-power hard real-time systems

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 697 - 702

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Darko Kirovski	Computer Science Department, University of California, Los Angeles, CA
Miodrag Potkonjak	Computer Science Department, University of California, Los Angeles, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 11, Downloads (12 Months): 103, Citation Count: 23

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ABSTRACT

We present a system-level approach for power optimization undera set of user specified costs and timing constraints of hard real-timedesigns. The approach optimizes all three degrees of freedom forpower minimization, namely switching activity, effective capacityand voltage supply.We first define two key associated optimization problems, processorallocation and task assignment, and establish their computationalcomplexity. Efficient algorithms are developed for bothsystem design problems. The statistical analysis of comprehensiveexperimental results and their comparison with the developed conservativeand optimistic sharp lower bounds, clearly indicates thequality of the proposed optimization techniques.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Yanbing Li , Jörg Henkel, A framework for estimating and minimizing energy dissipation of embedded HW/SW systems, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
	Jouml;rg Henkel , Yanbing Li, Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder, Proceedings of the 6th international workshop on Hardware/software codesign, p.23-27, March 15-18, 1998, Seattle, Washington, United States
	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Fast system-level power profiling for battery-efficient system design, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno, Cosimulation-based power estimation for system-on-chip design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.253-266, June 2002
	Dong-In Kang , Stephen Crago , Jinwoo Suh, Power-Aware Design Synthesis Techniques for Distributed Real-Time Systems, ACM SIGPLAN Notices, v.36 n.8, p.20-28, Aug. 2001
	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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	Marcus T. Schmitz , Bashir M. Al-Hashimi , Petru Eles, Iterative schedule optimization for voltage scalable distributed embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.182-217, February 2004
	B. P. Dave , N. K. Jha, CASPER: concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures, Proceedings of the conference on Design, automation and test in Europe, p.118-124, February 23-26, 1998, Le Palais des Congrés de Paris, France
	K. Masselos , K. Danckaert , F. Catthoor , N. Zervas , C. E. Goutis , H. De Man, A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints, Journal of VLSI Signal Processing Systems, v.26 n.3, p.291-317, Nov. 2000
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	Heng-Ruey Hsu , Jian-Jia Chen , Tei-Wei Kuo, Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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	Bharat P. Dave, CRUSADE: hardware/software co-synthesis of dynamically reconfigurable heterogeneous real-time distributed embedded systems, Proceedings of the conference on Design, automation and test in Europe, p.22-es, January 1999, Munich, Germany
	Li Shang , Niraj K. Jha, Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.345, January 07-11, 2002