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Layout driven re-synthesis for low power consumption LSIs
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 666 - 669  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
Masako Murofushi  Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
Takashi Ishioka  Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
Masami Murakata  Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
Takashi Mitsuhashi  Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 9,   Citation Count: 3
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ABSTRACT

A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Vaishnav and Massoud Pedram : "Pcube:A Performance Driven Placement Algorithm for Low Power Designs", Proc. European Desi9n Automation Conf., pp. 72-77 (1993).
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Mutsunori Igarashi, Masako Murofushi and Masami Murakata, "Timing Divert Placement with an RC wire Delay Model for Sub-Micron CMOS Gate-Arrays", SASIMI '93. (1993).


Collaborative Colleagues:
Masako Murofushi: colleagues
Takashi Ishioka: colleagues
Masami Murakata: colleagues
Takashi Mitsuhashi: colleagues