| Layout driven re-synthesis for low power consumption LSIs |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 666 - 669
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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Masako Murofushi
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Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
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Takashi Ishioka
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Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
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Masami Murakata
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Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
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Takashi Mitsuhashi
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Semiconductor DA & TEST Engineering Center, DA Development Dept., Kawasaki 210, Japan
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Downloads (6 Weeks): 5, Downloads (12 Months): 9, Citation Count: 3
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ABSTRACT
A new technology re-mapping method named LDR (LayoutDriven Re-synthesis), which is applied after placement, is proposed.LDR executes re-mapping and re-placement simultaneouslyin order to minimize power consumption with placementinformation.High switching activity nets are concealed insidethe re-mapped cells or are shortened by re-placement in LDR.To estimate power consumption, LDR uses static power estimatorfor combinational circuits.LDR also calculates wirecapacitances accurately based on placement information toevaluate power.Experimental results show that 20% powerreduction compared with original circuits is performed by proposed method.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Chi-Ying Tsui , Massoud Pedram , Alvin M. Despain, Technology decomposition and mapping targeting low power dissipation, Proceedings of the 30th international conference on Design automation, p.68-73, June 14-18, 1993, Dallas, Texas, United States
[doi> 10.1145/157485.164577]
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H. Vaishnav and Massoud Pedram : "Pcube:A Performance Driven Placement Algorithm for Low Power Designs", Proc. European Desi9n Automation Conf., pp. 72-77 (1993).
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Lalgudi N. Kannan , Peter R. Suaris , Hong-Gee Fang, A methodology and algorithms for post-placement delay optimization, Proceedings of the 31st annual conference on Design automation, p.327-332, June 06-10, 1994, San Diego, California, United States
[doi> 10.1145/196244.196399]
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Taku Uchino , Fumihiro Minami , Takashi Mitsuhashi , Nobuyuki Goto, Switching activity analysis using Boolean approximation method, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.20-25, November 05-09, 1995, San Jose, California, United States
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Mutsunori Igarashi, Masako Murofushi and Masami Murakata, "Timing Divert Placement with an RC wire Delay Model for Sub-Micron CMOS Gate-Arrays", SASIMI '93. (1993).
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CITED BY 3
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Wilm Donath , Prabhakar Kudva , Leon Stok , Lakshmi Reddy , Andrew Sullivan , Kanad Chakraborty , Paul Villarrubia, Transformational placement and synthesis, Proceedings of the conference on Design, automation and test in Europe, p.194-201, March 27-30, 2000, Paris, France
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