Post-layout logic restructuring for performance optimization

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Post-layout logic restructuring for performance optimization

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 662 - 665

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Yi-Min Jiang	Department of Electrical & Computer Engineering, University of California, Santa Barbara
Angela Krstic	Department of Electrical & Computer Engineering, University of California, Santa Barbara
Kwang-Ting Cheng	Department of Electrical & Computer Engineering, University of California, Santa Barbara
Malgorzata Marek-Sadowska	Department of Electrical & Computer Engineering, University of California, Santa Barbara

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 19

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

We propose a new methodology based on incrementallogic restructuring for post-layout performance improvement.The new post-layout logic restructuring techniqueallows to use accurate interconnection delays for performanceoptimization, while the incremental nature of thetechnique guarantees convergence between logic synthesisand layout. The technique can be further integrated withother post-layout optimization techniques such as gate sizingand buffer insertion. Experimental results show that thistechnique combined with post-layout buffer insertion canachieve an additional 15% improvement in performancecompared to designs produced by timing-driven logic optimizationfollowed by pre-layout buffer insertion followedby timing-driven physical design.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. Marek-Sadowska, "Issues in Timing Driven Layout," in Algorithmic Aspects of VLSI Layout, Edited by M. Sarrafzadeh and D. T. Lee, World Scientific Publishing Co., 1993.
	2	Robert J. Carragher , Masahiro Fujita , Chung-Kuan Cheng, Simple tree-construction heuristics for the fanout problem, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.671-679, October 02-04, 1995
	3	K.-T. Cheng and L. A. Entrena, "Multi-Level Logic Optimization by Redundancy Addition and Removal," Proceedings of European Design Automation Conference, pp. 373-377, February 1993.
	4	L.A. Entrena and K.-T. Cheng, "Sequential Logic Optimization by Redundancy Addition and Removal," IEEE Transactions on CAD, vol. 14, no. 7, pp. 909-916, July 1995.
	5	S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, "Perturb and Simplify: Multi-level Boolean Network Optimizer," IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.
	6	"SIS: A System for Sequential Circuit Synthesis," Report M92/ 41, University of California, Berkeley, May 1992.
	7	GARDS, "Command Reference Manual," Volume 1-4, Silicon Valley Research, September 1996.

CITED BY 19

	Chih-Wei Jim Chang , Malgorzata Marek-Sadowska, Who are the alternative wires in your neighborhood? (alternative wires identification without search), Proceedings of the 11th Great Lakes symposium on VLSI, p.103-108, March 2001, West Lafayette, Indiana, United States
	C. Chang , B. Hu , M. Marek-Sadowska, In-place delay constrained power optimization using functional symmetries, Proceedings of the conference on Design, automation and test in Europe, p.377-382, March 2001, Munich, Germany
	Wangning Long , Yu-Liang Wu , Jinian Bian, IBAW: an implication-tree based alternative-wiring logic transformation algorithm, Proceedings of the 2000 conference on Asia South Pacific design automation, p.415-422, January 2000, Yokohama, Japan
	Jason Cong , Yizhou Lin , Wangning Long, SPFD-based global rewiring, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Shih-Chieh Chang , Jung-Cheng Chuang , Zhong-Zhen Wu, Synthesis for multiple input wires replacement of a gate for wiring consideration, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.115-119, November 07-11, 1999, San Jose, California, United States
	Yanbin Jiang , Sachin S. Sapatnekar, An integrated algorithm for combined placement and libraryless technology mapping, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.102-106, November 07-11, 1999, San Jose, California, United States
	Ric Chung-Yang Huang , Yucheng Wang , Kwang-Ting Chen, LIBRA—a library-independent framework for post-layout performance optimization, Proceedings of the 1998 international symposium on Physical design, p.135-140, April 06-08, 1998, Monterey, California, United States
	Chih-Wei Jim Chang , Malgorzata Marek-Sadowska, ATPG-based logic synthesis: an overview, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.786-789, November 10-14, 2002, San Jose, California
	Jason Cong , Joey Y. Lin , Wangning Long, A new enhanced SPFD rewiring algorithm, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.672-678, November 10-14, 2002, San Jose, California
	Chih-Wei Chang , Chung-Kuan Cheng , Peter Suaris , Malgorzata Marek-Sadowska, Fast post-placement rewiring using easily detectable functional symmetries, Proceedings of the 37th conference on Design automation, p.286-289, June 05-09, 2000, Los Angeles, California, United States
	Katsunori Tanaka , Shigeru Yamashita , Yahiko Kambayashi, SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Chih Wei Jim Chang , Malgorzata Marek-Sadowska, Single-pass redundancy addition and removal, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Rüdiger Ebendt , Wolfgang Günther , Rolf Drechsler, Minimization of the expected path length in BDDs based on local changes, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.865-870, January 27-30, 2004, Yokohama, Japan
	Zhong-Zhen Wu , Shih-Chieh Chang, Multiple wire reconnections based on implication flow graph, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.939-952, October 2006
	Deshanand P. Singh , Stephen D. Brown, An area-efficient timing closure technique for FPGAs using Shannon's expansion, Integration, the VLSI Journal, v.40 n.2, p.167-173, February, 2007
	Kai-Chiang Wu , Diana Marculescu, Soft error rate reduction using redundancy addition and removal, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Kai-Hui Chang , Igor L. Markov , Valeria Bertacco, Postplacement rewiring by exhaustive search for functional symmetries, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-21, August 2007
	Hiroaki Yoshida , Motohiro Sera , Masao Kubo , Masahiro Fujita, Simultaneous Circuit Transformation and Routing, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.479, January 07-11, 2002
	Prashant Saxena , Vishal Khandelwal , Changge Qiao , Pei-Hsin Ho , J.-C. Lin , Mahesh A. Iyer, On improving optimization effectiveness in interconnect-driven physical synthesis, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA