Technology-dependent transformations for low-power synthesis

ABSTRACT

We propose a methodology for applying gate-level logictransformations to optimize power in digital circuits.Statisticallysimulated switching information, gate delays,signal arrival patterns, and signal probabilities are consideredin reducing the switching activity-capacitance products.Power reduction up to 45.4% (acerage 12.4%) is achieved,with considerable improvements in area and delay, in pre-optimizedbenchamarks.Also the effect of transformationson the random pattern testability of the circuits is studied.

REFERENCES

• 1: Brayton, et. al. Multilevel logic synthesis. Proc. of the IEEE, 1990, pp 264-300.
• 2: Chandrakasan, et. al. Optimizing power using transformations. IEEE Trans. on CAD of Integrated Circuits and Systems, 1995.
• 3: Goldstein. Controllability/observability analysis of digital circuits. IEEE Trans. on Circuits and Systems, CAS-26(9):685-693, 1979.
• 4: Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217537]
• 5: Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
• 6: S. Muroga , Y. Kambayashi , H. C. Lai , J. N. Culliney, The Transduction Method-Design of Logic Networks Based on Permissible Functions, IEEE Transactions on Computers, v.38 n.10, p.1404-1424, October 1989 [doi>10.1109/12.35836]
• 7: Najm. Transition Density : A new measure of activity in digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, pp 446-455.
• 8: Panda. Synthesis Techniques for VLSI Low-Power Circuits. PhD thesis, Univ. of Illinois at Urbana- Champaign, 1996.
• 9: Panda, et. al. Technology decomposition for low-power synthesis. CICC-95, pp 627-630.
• 10: Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth, Reducing power dissipation after technology mapping by structural transformations, Proceedings of the 33rd annual conference on Design automation, p.789-794, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240667]
• 11: Kaushik Roy , Sharat Prasad, SYCLOP: Synthesis of CMOS Logic for Low Power Applications, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.464-467, October 11-14, 1992
• 12: Tiwari, et. al. Compilation techniques for low energy: An overview. Syrup. on Low Power Elect., pp 38-39.
• 13: H. Ueda , K. Kinoshita, Low power design and its testability, Proceedings of the 4th Asian Test Symposium, p.361, November 23-24, 1995
• 14: Michael G. Xakellis , Farid N. Najm, Statistical estimation of the switching activity in digital circuits, Proceedings of the 31st annual conference on Design automation, p.728-733, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196628]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

Additional Classification:
  C. Computer Systems Organization

General Terms:
Design, Measurement, Performance, Theory