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Profile-driven program synthesis for evaluation of system power dissipation
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 576 - 581  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
Cheng-Ta Hsieh  Department of Electrical Engineering System, University of Southern California, Los Angeles, CA
Massoud Pedram  Department of Electrical Engineering System, University of Southern California, Los Angeles, CA
Gaurav Mehta  Mobile & Handheld Product Group, Intel Corporation, Santa Clara, CA
Fred Rastgar  Mobile & Handheld Product Group, Intel Corporation, Santa Clara, CA
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 16,   Citation Count: 15
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ABSTRACT

This paper presents a new approach for estimatingpower dissipation in a high performance microprocessor chip.First, characteristic profile (including parameters such as thecache miss rate, branch prediction miss rate, pipeline stalls,instruction mix, memory references, etc.) is extracted fromapplication programs. Then, mixed integer linear programmingand heuristic rules are used to gradually transform a genericprogram template to into a fully functional program. Thesynthesized program exhibits the same performance and powerdissipation behavior (as characterized by the extracted profile),yet it has an instruction trace orders of magnitude smaller thanthe initial trace. The synthesized program is subsequentlysimulated on a register-transfer level description of the targetmicroprocessor to provide the power dissipation value. Resultsobtained for the Intel's Pentium processor executing standardbenchmark programs show a simulation time reduction by 3-5orders of magnitude.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Toshinoriato, Yukio Otaguro, Masato Nagamatsu, and Haruyuki Tago. "Evaluation of architecture-level power estimation for CMOS RISC processors". In Proceedings of the Symposium on Low Power Electronics, pp. 44-45, 1995
 
2
Chih-Log Su, Chih-Ying Tsui, and Alvin M. Despain. "Low power architectures design and compilation techniques for high performance processors." In Proceedings of IEEE COMPCON, pp. 489-498, 1994
 
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Intel Corporation, "Pentium Processor Family Developer's Manual", Volume 1 :Pentium Processors, 1996

CITED BY  15

Collaborative Colleagues:
Cheng-Ta Hsieh: colleagues
Massoud Pedram: colleagues
Gaurav Mehta: colleagues
Fred Rastgar: colleagues