| Profile-driven program synthesis for evaluation of system power dissipation |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 576 - 581
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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Cheng-Ta Hsieh
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Department of Electrical Engineering System, University of Southern California, Los Angeles, CA
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Massoud Pedram
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Department of Electrical Engineering System, University of Southern California, Los Angeles, CA
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Gaurav Mehta
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Mobile & Handheld Product Group, Intel Corporation, Santa Clara, CA
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Fred Rastgar
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Mobile & Handheld Product Group, Intel Corporation, Santa Clara, CA
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Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 15
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ABSTRACT
This paper presents a new approach for estimatingpower dissipation in a high performance microprocessor chip.First, characteristic profile (including parameters such as thecache miss rate, branch prediction miss rate, pipeline stalls,instruction mix, memory references, etc.) is extracted fromapplication programs. Then, mixed integer linear programmingand heuristic rules are used to gradually transform a genericprogram template to into a fully functional program. Thesynthesized program exhibits the same performance and powerdissipation behavior (as characterized by the extracted profile),yet it has an instruction trace orders of magnitude smaller thanthe initial trace. The synthesized program is subsequentlysimulated on a register-transfer level description of the targetmicroprocessor to provide the power dissipation value. Resultsobtained for the Intel's Pentium processor executing standardbenchmark programs show a simulation time reduction by 3-5orders of magnitude.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Toshinoriato, Yukio Otaguro, Masato Nagamatsu, and Haruyuki Tago. "Evaluation of architecture-level power estimation for CMOS RISC processors". In Proceedings of the Symposium on Low Power Electronics, pp. 44-45, 1995
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Chih-Log Su, Chih-Ying Tsui, and Alvin M. Despain. "Low power architectures design and compilation techniques for high performance processors." In Proceedings of IEEE COMPCON, pp. 489-498, 1994
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Chi-Ying Tsui , Radu Marculescu , Diana Marculescu , Massoud Pedram, Improving the efficiency of power simulators by input vector compaction, Proceedings of the 33rd annual conference on Design automation, p.165-168, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240549]
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Diana Marculescu , Radu Marculescu , Massoud Pedram, Stochastic sequential machine synthesis targeting constrained sequence generation, Proceedings of the 33rd annual conference on Design automation, p.696-701, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240650]
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Intel Corporation, "Pentium Processor Family Developer's Manual", Volume 1 :Pentium Processors, 1996
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CITED BY 15
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Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
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Mehrdad Nourani , Joan Carletta , Christos Papachristou, Synthesis-for-testability of controller-datapath pairs that use gated clocks, Proceedings of the 37th conference on Design automation, p.613-618, June 05-09, 2000, Los Angeles, California, United States
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Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
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Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression for low power embedded system design, Proceedings of the 37th conference on Design automation, p.294-299, June 05-09, 2000, Los Angeles, California, United States
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