| A scheme for integrated controller-datapath fault testing |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 546 - 551
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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M. Nourani
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Dept. of Electrical & Computer Engineering, University of Tehran, Tehran, Iran
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J. Carletta
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Dept. of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
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C. Papachristou
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Dept. of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
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Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 8
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ABSTRACT
In systems consisting of interacting datapaths and controllersand utilizing built-in self test (BIST), the datapaths andcontrollers are traditionally tested separately by isolatingeach component from the environment of the system duringtest.This work facilitates the testing of datapath-controllerpairs in an integrated fashion.The key to the approach isthe addition of logic to the system that interacts with theexisting controller to push the effects of controller faults intothe data flow, so that they can be observed at the datapathregisters rather than directly at the controller outputs.Theresult is to reduce the BIST overhead over what is neededif the datapath and controller are tested independently, andto allow a more complete test of the interface between datapathand controller.Fault coverage and overhead resultsare given for four example circuits.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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M. Abadir and M. Breuer, "Constructing Optimal Test Schedules for VLSI Circuits Having Built-In Test Hardware," Intl. Conf. on Fault Tolerant Computation, June 1985.
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2
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3
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4
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Compass Design Automation, "User Manuals for COMPASS VLSI V8R4.4," Compass Design Automation, Inc., 1993.
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5
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Sujit Dey , Vijay Gangaram , Miodrag Potkonjak, A controller-based design-for-testability technique for controller-data path circuits, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.534-540, November 05-09, 1995, San Jose, California, United States
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6
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B. Eschermann and H. Wunderlich, "Optimized Synthesis of Self-Testable Finite State Machines," Intl. Co@ on Fault Tolerant Computation, 1990.
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7
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8
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AT&T, "User Manuals for GENTEST_S 2.0," AT&T Bell Laboratories, 1993.
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9
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10
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11
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12
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H. Harmanani , C. Papachristou , S. Chiu , M. Nourani, SYNTEST: an environment for system-level design for test, Proceedings of the conference on European design automation, p.402-407, November 1992, Congress Centrum Hamburg, Hamburg, Germany
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13
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14
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W.-B. Jone , C. A. Papachristou , M. Pereira, A scheme for overlaying concurrent testing of VLSI circuits, Proceedings of the 26th ACM/IEEE conference on Design automation, p.531-536, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74471]
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15
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16
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17
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D. Mukherejee, C. Njinda and M. Breuer, "Synthesis of Optimal l-hot Coded On-Chip Controllers for BIST Hardware," Proc. Intl. Conf. on Comp.-Aided Design, June 1991.
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18
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19
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L. Ramachandran and D. Gajski, "Behavioral Design Assistant (BdA) User's Manual, Version 1.0," UC / Irvine Tech. Report 9~-36, Sept. 1994.
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20
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CITED BY 8
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Mehrdad Nourani , Joan Carletta , Christos Papachristou, Synthesis-for-testability of controller-datapath pairs that use gated clocks, Proceedings of the 37th conference on Design automation, p.613-618, June 05-09, 2000, Los Angeles, California, United States
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Indradeep Ghosh , Niraj K. Jha , Sudipta Bhawmik, A BIST scheme for RTL controller-data paths based on symbolic testability analysis, Proceedings of the 35th annual conference on Design automation, p.554-559, June 15-19, 1998, San Francisco, California, United States
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Amir Attarha , Mehradad Nourani , Carco Lucas, Modeling and simulation of real defects using fuzzy logic, Proceedings of the 37th conference on Design automation, p.631-636, June 05-09, 2000, Los Angeles, California, United States
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J. Carletta , C. A. Papachristou , M. Nourani, Detecting undetectable controller faults using power analysis, Proceedings of the conference on Design, automation and test in Europe, p.723-728, March 27-30, 2000, Paris, France
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