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A scheme for integrated controller-datapath fault testing
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 546 - 551  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
M. Nourani  Dept. of Electrical & Computer Engineering, University of Tehran, Tehran, Iran
J. Carletta  Dept. of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
C. Papachristou  Dept. of Computer Engineering, Case Western Reserve University, Cleveland, Ohio
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Citation Count: 8
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ABSTRACT

In systems consisting of interacting datapaths and controllersand utilizing built-in self test (BIST), the datapaths andcontrollers are traditionally tested separately by isolatingeach component from the environment of the system duringtest.This work facilitates the testing of datapath-controllerpairs in an integrated fashion.The key to the approach isthe addition of logic to the system that interacts with theexisting controller to push the effects of controller faults intothe data flow, so that they can be observed at the datapathregisters rather than directly at the controller outputs.Theresult is to reduce the BIST overhead over what is neededif the datapath and controller are tested independently, andto allow a more complete test of the interface between datapathand controller.Fault coverage and overhead resultsare given for four example circuits.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
M. Abadir and M. Breuer, "Constructing Optimal Test Schedules for VLSI Circuits Having Built-In Test Hardware," Intl. Conf. on Fault Tolerant Computation, June 1985.
 
2
 
3
 
4
Compass Design Automation, "User Manuals for COMPASS VLSI V8R4.4," Compass Design Automation, Inc., 1993.
 
5
 
6
B. Eschermann and H. Wunderlich, "Optimized Synthesis of Self-Testable Finite State Machines," Intl. Co@ on Fault Tolerant Computation, 1990.
 
7
 
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AT&T, "User Manuals for GENTEST_S 2.0," AT&T Bell Laboratories, 1993.
 
9
10
 
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D. Mukherejee, C. Njinda and M. Breuer, "Synthesis of Optimal l-hot Coded On-Chip Controllers for BIST Hardware," Proc. Intl. Conf. on Comp.-Aided Design, June 1991.
 
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L. Ramachandran and D. Gajski, "Behavioral Design Assistant (BdA) User's Manual, Version 1.0," UC / Irvine Tech. Report 9~-36, Sept. 1994.
 
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CITED BY  8

Collaborative Colleagues:
M. Nourani: colleagues
J. Carletta: colleagues
C. Papachristou: colleagues