Transistor sizing issues and tool for multi-threshold CMOS technology

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Transistor sizing issues and tool for multi-threshold CMOS technology

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 409 - 414

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

James Kao	Department of EECS, Massachusetts Institute of Technology, Cambridge
Anantha Chandrakasan	Department of EECS, Massachusetts Institute of Technology, Cambridge
Dimitri Antoniadis	Department of EECS, Massachusetts Institute of Technology, Cambridge

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 18, Downloads (12 Months): 72, Citation Count: 42

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ABSTRACT

Multi-threshold CMOS is an increasingly popular circuitapproach that enables high performance and low power operation.However, no methodologies have been developed to size the highV{t} sleep transistor in an intelligent manner that trades off area andperformance. In fact, many attempts at sizing the sleep transistorwithout close consideration of input vector patterns or internalstructures can lead to large overestimates or large underestimatesin sleep transistor sizing. This paper describes some of the issuesinvolved in sizing transistors for MTCMOS and also introduces avariable breakpoint switch level simulator that can rapidly calculatedelay in MTCMOS circuits as functions of design variablessuch as V{dd}, V{t}, and sleep transistor sizing.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Mircea R. Stan, Low threshold CMOS circuits with low standby current, Proceedings of the 1998 international symposium on Low power electronics and design, p.97-99, August 10-12, 1998, Monterey, California, United States
	Zhanping Chen , Liqiong Wei , Kaushik Roy, On effective I_DDQ Testing of low-voltage CMOS circuits using leakage control techniques, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.718-725, October 2001
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002
	James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States
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