Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

ABSTRACT

We demonstrate a new approach minimizing the total ofthe static and the dynamic power dissipation components in aCMOS logic network required to operate at a specified clockfrequency using joint optimization of both device and circuitdesigns for a specific logic schematic and activity profile.We present a new approach to designing ultra low-powerCMOS logic circuits by joint optimization of supply voltage,threshold voltage and device widths for a specified speedconstraints.The static (leakage) and dynamic (switching)energy components are considered and an efficient heuristicis developed that delivers over an order of magnitude savingsin power over conventional optimization methods.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.3 Design Aids
          Subjects: Optimization

  C. Computer Systems Organization

General Terms:
Algorithms, Design, Measurement, Performance, Theory