Vector generation for maximum instantaneous current through supply lines for CMOS circuits

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Vector generation for maximum instantaneous current through supply lines for CMOS circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 383 - 388

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Angela Krstić	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
Kwang-Ting Cheng	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 25

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ABSTRACT

We present two new algorithms for generating a smallset of patterns for estimating the maximum instantaneouscurrent through the power supply lines for CMOScircuits.The first algorithm is based on timed ATPG,while the second is a probability-based approach.Bothalgorithms can handle circuits with arbitrary but knowndelays and they produce a set of 2-vector tests.Experimentalresults demonstrating that the outcome of applyingour algorithms is a small set of patterns producinga current that is a tight lower bound on the maximuminstantaneous current are included.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Y.-M. Jiang , K.-T. Cheng, Exact and approximate estimation for maximum instantaneous current of CMOS circuits, Proceedings of the conference on Design, automation and test in Europe, p.698-703, February 23-26, 1998, Le Palais des Congrés de Paris, France
	R. Saleh , D. Overhauser , S. Taylor, Full-chip verification of UDSM designs, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.453-460, November 08-12, 1998, San Jose, California, United States
	Yi-Min Jiang , Kwang-Ting Cheng , An-Chang Deng, Estimation of maximum power supply noise for deep sub-micron designs, Proceedings of the 1998 international symposium on Low power electronics and design, p.233-238, August 10-12, 1998, Monterey, California, United States
	Mustafa Badaroglu , Kris Tiri , StÉphane Donnay , Piet Wambacq , Hugo De Man , Ingrid Verbauwhede , Georges Gielen, Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Rajat Chaudhry , David Blaauw , Rajendran Panda , Tim Edwards, Current signature compression for IR-drop analysis, Proceedings of the 37th conference on Design automation, p.162-167, June 05-09, 2000, Los Angeles, California, United States
	Gregory Steele , David Overhauser , Steffen Rochel , Syed Zakir Hussain, Full-chip verification methods for DSM power distribution systems, Proceedings of the 35th annual conference on Design automation, p.744-749, June 15-19, 1998, San Francisco, California, United States
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