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Synthesis of application specific programmable processors
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 353 - 358  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
Kyosun Kim  Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
Ramesh Karri  Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
Miodrag Potkonjak  Department of Computer Science, University of California, Los Angeles, CA
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 16,   Citation Count: 12
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ABSTRACT

Synthesis of Application Specific ProgrammableProcessors poses numerous new tasks onbehavioral synthesis tools.We address some ofthem including application bundling.ApplicationBundling is a synthesis task where n control-data flowgraphs are bundled into at most m groups, so that eachapplication belongs to at least one group and throughputconstraints for all applications are satisfied.We have shown how a variety of application specificconstraints such as manufacturing cost reduction andproduction risk reduction can be targeted during thesynthesis process.The effectiveness of our approach isdemonstrated on a number of real examples.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. C. McFarland and A. C. Parker and R. Camposano, "The high-level synthesis of digital systems", Proc of IEEE, Vol. 78, No. 2, pp. 301-318, 1990.
 
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A. E1 Gamal, J. Rose, A. Sangiovanni-Vincentelli, "Synthesis Methods for Field Programmable Gate Arrays", Proc. of IEEE, pp. 1013-1029, 1993.
 
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G.D. Hillman: "DSP56200: An Algorithm-Specific Digital Signal Processor Peripheral", Proc. of IEEE, pp. 1185-1191, 1987.
 
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A.K. Yeung, J.M. Rabaey, "A 2.4 GOPS data-driven reconfigurable multiprocessor IC for DSP", ISSCC, pp. 108-109, 1995.

CITED BY  12

Collaborative Colleagues:
Kyosun Kim: colleagues
Ramesh Karri: colleagues
Miodrag Potkonjak: colleagues