| CELLERITY: a fully automatic layout synthesis system for standard cell libraries |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 327 - 332
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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Mohan Guruswamy
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Robert L. Maziasz
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Daniel Dulitz
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Srilata Raman
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Venkat Chiluvuri
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Andrea Fernandez
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Larry G. Jones
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Unified Design System Laboratory, Motorola, Inc., Austin, Texas
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Downloads (6 Weeks): 2, Downloads (12 Months): 25, Citation Count: 5
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ABSTRACT
This paper describes a fully automatic standard-cell layoutsynthesis system, CELLERITY. The system is flexible insupporting a wide variety of process technologies and a range oflibrary template styles. The tool is fully automatic and providesseveral options to the user to customize the layout template. Thetool considers performance and yield and generates dense,design-rule correct layouts. Experimental results indicate that thearea of CELLERITY-generated standard cells is competitive withmanually designed cells in a majority of circuits. In block-leveltests of industrial circuits, standard-cell blocks generated usingCELLERITY cells are about equal to the block area produced byusing a manually-designed library. Recently, an embeddedmicrocontroller in a state-of-the-art sub-micron processtechnology was fabricated using CELLERITY-generated standard cells.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 5
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S. Gavrilov , A. Glebov , S. Pullela , S. C. Moore , A. Dharchoudhury , R. Panda , G. Vijayan , D. T. Blaauw, Library-less synthesis for static CMOS combinational logic circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.658-662, November 09-13, 1997, San Jose, California, United States
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