ACM Home Page
Please provide us with feedback. Feedback
CAD at the design-manufacturing interface
Full text PdfPdf (193 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 321 - 326  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
H. T. Heineken  Level One Communications, Sacramento, CA and ECE Dept., Carnegie Mellon University, Pittsburgh, PA
J. Khare  Level One Communications, Sacramento, CA and ECE Dept., Carnegie Mellon University, Pittsburgh, PA
W. Maly  ECE Dept., Carnegie Mellon University, Pittsburgh, PA
P. K. Nag  ECE Dept., Carnegie Mellon University, Pittsburgh, PA
C. Ouyang  ECE Dept., Carnegie Mellon University, Pittsburgh, PA
W. A. Pleskacz  ECE Dept., Carnegie Mellon University, Pittsburgh, PA and Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Poland
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 19,   Citation Count: 6
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/266021.266123
What is a DOI?

ABSTRACT

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
W. Maly: Ed., "Design for manufacturability for next decade," CMU-SRC Research Report No. CMUCAD-97-10, Pittsburgh, USA, March 1997.
 
4
H.T. Heineken and W. Maly, "Manufacturability analysis environment - MAPEX," Custom Integrated Circuits Conference, pp. 309-312, May 1994
 
5
Dracula 4.1, Reference Manual Set, Cadence Design Systems Inc., San Jose, CA, 1993.
 
6
S-Plus 3.1, Reference Manual Set, Statistical Science Inc., Seattle, WA, Oct. 1992.
 
7
 
8
W. Maly and J. Deszczka, "Yield estimation model for VLSI artwork evaluations," Electron. Lett., vol. 19, no. 6, pp. 226- 227, March 1983.
 
9
 
10
A.V. Ferris-Prabhu, "Modeling the critical area in yield forecasts," IEEE J. Solid-State Circuits, vol. SC-20, no. 4, pp. 874-878, Aug. 1985.
 
11
W. Maly, "Computer-aided design for VLSI circuit manufacturability," Proc. of the IEEE, vol. 78, no. 25, pp. 356-392, Feb. 1990.
 
12
H.T. Heineken, J. Khare, and W. Maly, "Yield loss forecasting in the early phases of the VLSI design process," Custom Integrated Circuits Conference, pp. 27-30, May 1996.
 
13
 
14
 
15
 
16
 
17
D. Schmitt-Landsiedel, D. Keitel-Schulz, J. Khare, S. Griep, and W. Maly, "Critical area analysis for design-based yield improvement of VLSI circuits," Quality and Reliability Engineering International, Vol. 11, pp. 227-232, 1995.
 
18
S. Fang and J. McVittie, "Thin-oxide damage from gate charging during plasma processing," IEEE Elect~vn Device Letters, vol. 13, no. 5, p. 288, May 1992.
 
19
 
20
 
21
M. Pedram and B. Preas, "Interconnection length estimation for optimized standard cell layouts," Int. Conference on Computer-Aided Design, pp. 390-393, Nov. 1989.


Collaborative Colleagues:
H. T. Heineken: colleagues
J. Khare: colleagues
W. Maly: colleagues
P. K. Nag: colleagues
C. Ouyang: colleagues
W. A. Pleskacz: colleagues