Generation of software tools from processor descriptions for hardware/software codesign

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Generation of software tools from processor descriptions for hardware/software codesign

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 303 - 306

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Mark R. Hartoog	Alta Group of Cadence Design Systems, Inc.
James A. Rowson	Alta Group of Cadence Design Systems, Inc.
Prakash D. Reddy	Alta Group of Cadence Design Systems, Inc.
Soumya Desai	Alta Group of Cadence Design Systems, Inc.
Douglas D. Dunlop	Alta Group of Cadence Design Systems, Inc.
Edwin A. Harcourt	Alta Group of Cadence Design Systems, Inc.
Neeti Khullar	Alta Group of Cadence Design Systems, Inc.

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 29, Citation Count: 25

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

An experimental set of tools that generate instruction set simulators,assemblers, and disassemblers from a single description wasdeveloped to test if retargetable development tools would work forcommercial DSP processors and microprocessors. The processorinstruction set was described using a language called nML. TheTMS320C50 DSP processor and the ARM7 microprocessor weremodeled in nML. The resulting instruction set models executeabout 25,000 instructions per second, and compiled instruction setsimulation models execute about 150,000 instructions per second.The viability of this approach and the deficiencies of nML are discussed.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 25

	Rainer Laupers, HDL-based modeling of embedded processor behavior for retargetable compilation, Proceedings of the 11th international symposium on System synthesis, p.51-54, December 02-04, 1998, Hsinchu, Taiwan, China
	Gunnar Braun , Andreas Hoffmann , Achim Nohl , Heinrich Meyr, Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine description, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Stefan Pees , Andreas Hoffmann , Vojin Zivojnovic , Heinrich Meyr, LISA—machine description language for cycle-accurate models of programmable DSP architectures, Proceedings of the 36th ACM/IEEE conference on Design automation, p.933-938, June 21-25, 1999, New Orleans, Louisiana, United States
	Chuck Siska, A processor desription language supporting retargetable multi-pipeline DSP program development tools, Proceedings of the 11th international symposium on System synthesis, p.31-36, December 02-04, 1998, Hsinchu, Taiwan, China
	Stefan Pees , Andreas Hoffmann , Heinrich Meyr, Retargeting of compiled simulators for digital signal processors using a machine description language, Proceedings of the conference on Design, automation and test in Europe, p.669-673, March 27-30, 2000, Paris, France
	Jianwen Zhu , Daniel D. Gajski, An ultra-fast instruction set simulator, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.363-373, June 2002
	Wai Sum Mong , Jianwen Zhu, A retargetable micro-architecture simulator, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Mehrdad Reshadi , Nikhil Bansal , Prabhat Mishra , Nikil Dutt, An efficient retargetable framework for instruction-set simulation, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	George Hadjiyiannis , Srinivas Devadas, Techniques for accurate performance evaluation in architecture exploration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.601-615, August 2003
	George Hadjiyiannis , Pietro Russo , Srinivas Devadas, A methodology for accurate performance evaluation in architecture exploration, Proceedings of the 36th ACM/IEEE conference on Design automation, p.927-932, June 21-25, 1999, New Orleans, Louisiana, United States
	Stefan Pees , Andreas Hoffmann , Heinrich Meyr, Retargetable compiled simulation of embedded processors using a machine description language, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.4, p.815-834, Oct. 2000
	A. Hoffmann , A. Nohl , S. Pees , G. Braun , H. Meyr, Generating production quality software development tools using a machine description language, Proceedings of the conference on Design, automation and test in Europe, p.674-678, March 2001, Munich, Germany
	Andreas Hoffmann , Oliver Schliebusch , Achim Nohl , Gunnar Braun , Oliver Wahlen , Heinrich Meyr, A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Gunnar Braun , Achim Nohl , Weihua Sheng , Jianjiang Ceng , Manuel Hohenauer , Hanno Scharwächter , Rainer Leupers , Heinrich Meyr, A novel approach for flexible and consistent ADL-driven ASIP design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Scott J. Weber , Matthew W. Moskewicz , Matthias Gries , Christian Sauer , Kurt Keutzer, Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	Achim Nohl , Gunnar Braun , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Andreas Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Mehrdad Reshadi , Prabhat Mishra , Nikil Dutt, Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Rodolfo Azevedo , Sandro Rigo , Marcus Bartholomeu , Guido Araujo , Cristiano Araujo , Edna Barros, The ArchC architecture description language and tools, International Journal of Parallel Programming, v.33 n.5, p.453-484, October 2005
	In-Cheol Park , Sehyeon Kang , Yongseok Yi, Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.138, November 09-13, 2003
	Mehrdad Reshadi , Nikil Dutt , Prabhat Mishra, A retargetable framework for instruction-set architecture simulation, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.2, p.431-452, May 2006
	M. Poncino , Jianwen Zhu, DynamoSim: a trace-based dynamically compiled instruction set simulator, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.131-136, November 07-11, 2004
	M. Poncino , Jianwen Zhu, DynamoSim: a trace-based dynamically compiled instruction set simulator, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.131-136, November 07-11, 2004
	Oliver Schliebusch , Andreas Hoffmann , Achim Nohl , Gunnar Braun , Heinrich Meyr, Architecture Implementation Using the Machine Description Language LISA, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.239, January 07-11, 2002
	Alexandro Baldassin , Paulo Centoducatte , Sandro Rigo , Daniel Casarotto , Luiz C. V. Santos , Max Schultz , Olinto Furtado, An open-source binary utility generator, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.2, p.1-17, April 2008
	Mehrdad Reshadi , Prabhat Mishra , Nikil Dutt, Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.3, p.1-27, April 2009