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ABSTRACT
We present the Instruction Set Description Language,ISDL, a machine description language used to describetarget architectures to a retargetable compiler. The featuresand flexibility of ISDL enable the description of vastly differentarchitectures, in particular VLIW architectures. ISDL explicitlysupports constraints that define valid operation groupingswithin an instruction, increasing the range of specifiable architectures.We have written a tool that, given an ISDL descriptionof a processor, automatically generates an assembler forit. Ongoing work includes the development of an automaticcode-generator generator.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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2
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3
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D. Lanneer et al. CHESS: Retargetable Code Generation for Embedded DSP Processors. In Code Generation for Embedded Processors, pages 85-102. Kluwer Academic Publishers, 1995.
|
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4
|
|
| |
5
|
P. Marwedel and G. Goossens, editors. Code Generation for Embedded Processors. Kluwer Academic Publishers, Boston, Massachusetts, 1995. Proceedings of the 1994 Dagstuhl Workshop on Code Generation for Embedded Processors. ISBN 0-7923-9577-8.
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| |
6
|
Gert Goossens , Dirk Lanneer , Marc Pauwels , Francis Depuydt , Koen Schoofs , Augusli Kifli , Marco Cornero , Paolo Petroni , Francky Catthoor , Hugo De Man, Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures, Journal of VLSI Signal Processing Systems, v.9 n.1-2, p.49-65, Jan. 1995
[doi> 10.1007/BF02406470]
|
| |
7
|
A. Fauth, J. Van Praet, and M. Freericks. Describing Instruction Sets Using nML (Extended Version). Technical report, Technische Universit~it Berlin and IMEC, Berlin (Germany)/Leuven (Belgium), 1995.
|
| |
8
|
Pierre G. Paulin , Clifford Liem , Trevor C. May , Shailesh Sutarwala, CodeSyn: a retargetable code synthesis system (abstract), Proceedings of the 7th international symposium on High-level synthesis, p.94, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
|
| |
9
|
|
| |
10
|
Stanford Compiler Group. The SUIF Libra,7, version 1.0 edition, 1994.
|
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11
|
G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. Technical report, MIT, 1996. (http://rlevlsi.mit.edu/spam/pubs/ISDL-TR.html).
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Albert Wang , Earl Killian , Dror Maydan , Chris Rowen, Hardware/software instruction set configurability for system-on-chip processors, Proceedings of the 38th conference on Design automation, p.184-188, June 2001, Las Vegas, Nevada, United States
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Naji Ghazal , Richard Newton , Jan Rabaey, Predicting performance potential of modern DSPs, Proceedings of the 37th conference on Design automation, p.332-335, June 05-09, 2000, Los Angeles, California, United States
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Stefan Pees , Andreas Hoffmann , Vojin Zivojnovic , Heinrich Meyr, LISA—machine description language for cycle-accurate models of programmable DSP architectures, Proceedings of the 36th ACM/IEEE conference on Design automation, p.933-938, June 21-25, 1999, New Orleans, Louisiana, United States
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Stefan Pees , Andreas Hoffmann , Heinrich Meyr, Retargeting of compiled simulators for digital signal processors using a machine description language, Proceedings of the conference on Design, automation and test in Europe, p.669-673, March 27-30, 2000, Paris, France
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Peter Grun , Nikil Dutt , Alex Nicolau, Memory aware compilation through accurate timing extraction, Proceedings of the 37th conference on Design automation, p.316-321, June 05-09, 2000, Los Angeles, California, United States
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Achim Nohl , Volker Greive , Gunnar Braun , Andreas Andreas , Rainer Leupers , Oliver Schliebusch , Heinrich Meyr, Instruction encoding synthesis for architecture exploration using hierarchical processor models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Mehrdad Reshadi , Nikhil Bansal , Prabhat Mishra , Nikil Dutt, An efficient retargetable framework for instruction-set simulation, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
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Silvina Hanono , Srinivas Devadas, Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator, Proceedings of the 35th annual conference on Design automation, p.510-515, June 15-19, 1998, San Francisco, California, United States
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Q. Zhao , T. Basten , B. Mesman , C. A. J. van Eijk , J. A. G. Jess, Static resource models of instruction sets, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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George Hadjiyiannis , Pietro Russo , Srinivas Devadas, A methodology for accurate performance evaluation in architecture exploration, Proceedings of the 36th ACM/IEEE conference on Design automation, p.927-932, June 21-25, 1999, New Orleans, Louisiana, United States
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A. Hoffmann , A. Nohl , S. Pees , G. Braun , H. Meyr, Generating production quality software development tools using a machine description language, Proceedings of the conference on Design, automation and test in Europe, p.674-678, March 2001, Munich, Germany
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Andreas Hoffmann , Oliver Schliebusch , Achim Nohl , Gunnar Braun , Oliver Wahlen , Heinrich Meyr, A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
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Gunnar Braun , Achim Nohl , Weihua Sheng , Jianjiang Ceng , Manuel Hohenauer , Hanno Scharwächter , Rainer Leupers , Heinrich Meyr, A novel approach for flexible and consistent ADL-driven ASIP design, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
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Scott J. Weber , Matthew W. Moskewicz , Matthias Gries , Christian Sauer , Kurt Keutzer, Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
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Achim Nohl , Gunnar Braun , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Andreas Hoffmann, A universal technique for fast and flexible instruction-set architecture simulation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Oliver Schliebusch , A. Chattopadhyay , D. Kammler , G. Ascheid , R. Leupers , H. Meyr , Tim Kogel, A framework for automated and optimized ASIP implementation supporting multiple hardware description languages, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Rodolfo Azevedo , Sandro Rigo , Marcus Bartholomeu , Guido Araujo , Cristiano Araujo , Edna Barros, The ArchC architecture description language and tools, International Journal of Parallel Programming, v.33 n.5, p.453-484, October 2005
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Jianjiang Ceng , Weihua Sheng , Manuel Hohenauer , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Gunnar Braun, Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting, Journal of VLSI Signal Processing Systems, v.43 n.2-3, p.235-246, June 2006
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Sanghyun Park , Eugene Earlie , Aviral Shrivastava , Alex Nicolau , Nikil Dutt , Yunheung Paek, Automatic generation of operation tables for fast exploration of bypasses in embedded processors, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Sandro Rigo , Marcio Juliato , Rodolfo Azevedo , Guido Araújo , Paulo Centoducatte, Teaching computer architecture using an architecture description language, Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture, June 19, 2004, Munich, Germany
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Ashok Halambi , Peter Grun , Vijay Ganesh , Asheesh Khare , Nikil Dutt , Alex Nicolau, EXPRESSION: a language for architecture exploration through compiler/simulator retargetability, Proceedings of the conference on Design, automation and test in Europe, p.100-es, January 1999, Munich, Germany
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Gunnar Braun , Andreas Wieferink , Oliver Schliebusch , Rainer Leupers , Heinrich Meyr , Achim Nohl, Processor/Memory Co-Exploration on Multiple Abstraction Levels, Proceedings of the conference on Design, Automation and Test in Europe, p.10966, March 03-07, 2003
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Prabhat Mishra , Ashok Halambi , Peter Grun , Nikil Dutt , Alex Nicolau , Hiroyuki Tomiyama, Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.458, January 07-11, 2002
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Oliver Schliebusch , A. Chattopadhyay , R. Leupers , G. Ascheid , H. Meyr , Mario Steinert , Gunnar Braun , Achim Nohl, RTL Processor Synthesis for Architecture Exploration and Implementation, Proceedings of the conference on Design, automation and test in Europe, p.30156, February 16-20, 2004
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B. Mei , B. Sutter , T. Aa , M. Wouters , A. Kanstein , S. Dupont, Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder, Journal of Signal Processing Systems, v.51 n.3, p.225-243, June 2008
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Rola Kassem , Mikaël Briday , Jean-Luc Béchennec , Yvon Trinquet , Guillaume Savaton, Instruction set simulator generation using HARMLESS, a new hardware architecture description language, Proceedings of the 2nd International Conference on Simulation Tools and Techniques, March 02-06, 2009, Rome, Italy
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