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Formal verification in a commercial setting
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 258 - 262  
Year of Publication: 1997
ISBN:0-89791-920-3
Author
R. P. Kurshan  Bell Laboratories, Murray Hill, NJ
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 17,   Citation Count: 16
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ABSTRACT

This tutorial addresses the following questions:¿ why do formal verification?¿ who is doing it today?¿ what are they doing?¿ how are they doing it?¿ what about the future?


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J.R. Burch, E. M. Clarke, D. Long, K. L. McMillan, D. L. Dill, Symbolic Model Checking for Sequential Circuit Verification, IEEE Trans. Computer Aided Design, 13 (1994) 401-424.
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R. H. Hardin, Z. Har'E1, R. P. Kurshan, COSPAN, Springer LNCS 1102 (1996) 423-427.
 
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CITED BY  16