Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling

ABSTRACT

A hierarchical two-dimensional field solution technique isintroduced for capacitance extraction for VLSI interconnectmodeling. As a basis for compromise between the efficiencyof Boolean rules-based extraction and the accuracy of flatfield solution, this hierarchical approach can handlerealistic conductor cross-sections and multiple conformaland/or planarized dielectrics.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS
      G.1.4 Quadrature and Numerical Differentiation
          Subjects: Finite difference methods

General Terms:
Design, Measurement, Performance, Theory