Optimizing designs containing black boxes

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Optimizing designs containing black boxes

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 113 - 116

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Tai-Hung Liu	Electrical and Computer Engineering, The University of Texas, Austin TX
Khurram Sajid	Electrical and Computer Engineering, The University of Texas, Austin TX
Adnam Aziz	Electrical and Computer Engineering, The University of Texas, Austin TX
Vigyan Singhal	Cadence Berkeley Labs, Cadence, Berkeley, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 10, Citation Count: 4

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

We define a notion of equivalence for designs containingblack boxes i.e., components whose functionality is notknown; these arise naturally in the course of hierarchicaldesign. Using this notion, we describe a sound andcomplete methodology for optimizing such designs.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. P. Appenzeller, Formal verification of a PowerPC microprocessor, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.79, October 02-04, 1995
	2	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	3	Jerry R. Burch , David Dill , Elizabeth Wolf , Giovanni de Micheli, Modeling hierarchical combinational circuits, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.612-617, November 07-11, 1993, Santa Clara, California, United States
	4	M. Damiani and G. De Micheli. Don't care Set Specifications in Combinational and Synchronous Logic Circuits. Technical Report CSL-TR-92-531, Stanford University, Computer Systems Laboratory, Stanford, CA 94305-4055, July 1992.
	5	L. Stok , D. S. Kung , D. Brand , A. D. Drumm , L. N. Reddy , N. Hieter , D. J. Geiger , H. H. Chao , P. J. Osler , A. J. Sullivan, BooleDozer: logic synthesis for ASICs, IBM Journal of Research and Development, v.40 n.4, p.407-430, July 1996
	6	John E. Hopcroft , Jeffrey D. Ullman, Introduction To Automata Theory, Languages, And Computation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	7	Tai-Hung Liu. church, ece. utexas, edu/ -tai/dac-bb-97 .ps.
	8	David Esley Long, Model checking, abstraction, and compositional verification, Carnegie Mellon University, Pittsburgh, PA, 1993
	9	S. Malik. Analysis of Cyclic Combinational Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 13(7):950-956, July 1994.
	10	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	11	Hamid Savoj, Don't cares in multi-level network optimization, University of California at Berkeley, Berkeley, CA, 1992
	12	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	13	Robert E. Shostak, A Practical Decision Procedure for Arithmetic with Function Symbols, Journal of the ACM (JACM), v.26 n.2, p.351-360, April 1979 [doi>10.1145/322123.322137]
	14	Vigyan Singhal , Robert K. Brayton, Design replacements for sequential circuits, 1996

CITED BY 4

	Darko Kirovski , Yean-Yow Hwang , Miodrag Potkonjak , Jason Cong, Intellectual property protection by watermarking combinational logic synthesis solutions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.194-198, November 08-12, 1998, San Jose, California, United States
	Tai-Hung Liu , Adnan Aziz , Vigyan Singhal, Optimizing designs containing black boxes, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.4, p.591-601, October 2001
	Ilia Polian , Wolfgang Günther , Bernd Becker, Pattern-based verification of connections to intellectual property cores, Integration, the VLSI Journal, v.35 n.1, p.25-44, June 2003
	Yunjian Jiang , Robert K. Brayton, Don't cares in logic minimization of extended finite state machines, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan