A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications

ABSTRACT

In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues to engineeringchanges is the turn-around time. Ideally, after designers modify their designs, they resume their debugging and verification tasks immediately. However, converting a design from its Register-Transfer-Level (RTL) description to a target emulator is a time-consuming procedure which may take hours. Such long engineering-change turn-around times are unacceptable by the designers. In this paper, we present a real-time RTLengineering-change method supporting on-line debuggingfor logic-emulation applications. We propose a novel design method which is able to link design data generated at different design stages in a unified way. Using thismethod, the users can immediately locate the portion ofthe circuit design affected by the design modification fromits RTL specification. This feature provides users with afast time-to-debug environment by significantly improving the efficiency of the engineering-change process. We have developed aprototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the effectiveness of the proposed method.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

  J. Computer Applications

General Terms:
Design, Experimentation, Measurement, Performance, Theory, Verification