A C-based RTL design verification methodology for complex microprocessor

ABSTRACT

As the complexity of high-performance microprocessor increases,functional verification becomes more and more difficultand RTL simulation emerges as the bottleneck of thedesign cycle.In this paper, we suggest C language-based designand verification methodology to enhance the simulationspeed instead of the conventional HDL-based methodologies.RTL C model (StreC) describes the cycle-based behaviors ofsynchronous circuits and is followed by model refining andoptimization using LifeTime Analyzer (LTA) and Cleaner.The simulation speed of cycle-based C model makes it possibleto test the RTL design with the "real-world" applicationprograms in the order-of-magnitude faster speed thanthe commercial event-driven simulators.Using the proposedfunctional verification methodology, HK486, an intel 80486 - compatiblemicroprocessor was successfully designed and verified.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Hardware description languages

  C. Computer Systems Organization

  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.2 Language Classifications

          Nouns: C

General Terms:
Design, Languages, Performance, Reliability, Theory, Verification