Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

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Data memory minimisation for synchronous data flow graphs emulated on DSP-FPGA targets

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 64 - 69

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Marleen Adé	Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
Rudy Lauwereins	Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium
J. A. Peperstraete	Katholieke Universiteit Leuven, ESAT Department, ACCA Laboratory, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 23, Citation Count: 10

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

The paper presents an algorithm to determine the close-to-smallestpossible data buffer sizes for arbitrary synchronous dataflow (SDF) applications, such that we can guarantee the existenceof a deadlock free schedule. The presented algorithm fits inthe design flow of GRAPE, an environment for the emulation andimplementation of digital signal processing (DSP) systems onarbitrary target architectures, consisting of programmable DSPprocessors and FPGAs. Reducing the size of data buffers is ofhigh importance when the application will be mapped on FieldProgrammable Gate Arrays (FPGA), since register resources arerather scarce.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Rudy Lauwereins , Marc Engels , Marleen Adé , J. a. Peperstraete, Grape-II: A System-Level Prototyping Environment for DSP Applications, Computer, v.28 n.2, p.35-43, February 1995 [doi>10.1109/2.347998]
	2	J. Buck, S. Ha, E.A. Lee, D.G. Messerschmitt, "Ptolemy: a Framework for Simulating and Prototyping Heterogeneous Systems", Int. Journal of Computer Simulation, Vol. 4, April 1994, pp. 155-182.
	3	Synopsys Inc., 700 E. Middlefield Rd., Mountain View, CA 94043, USA, COSSAP User's Manual.
	4	Greet Bilsen, Marc Engels, Rudy Lauwereins, J.A. Peperstraete, "Cyclo-Static Dataflow", IEEE Transactions on Signal Processing, Vol. 44, No. 2, Feb. 1996, pp. 397-408.
	5	Edward Ashford Lee , David G. Messerschmitt, Static scheduling of synchronous data flow programs for digital signal processing, IEEE Transactions on Computers, v.36 n.1, p.24-35, Jan. 1987 [doi>10.1109/TC.1987.5009446]
	6	Greet Bilsen, Marc Engels, Rudy Lauwereins, J.A. Peperstraete, "Compile-time Makespan-optimal Multi-resource Mapping for Hardware/Software Co-design", KULeuven Technical Report ESAT-ACCA 95-02.
	7	M. Ade , R. Lauwereins , J. A. Peperstraete, Hardware-software codesign with GRAPE, Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95), p.40, June 07-09, 1995
	8	S. S. Bhattacharyya , P. K. Murthy , E. A. Lee, Converting graphical DSP programs into memory constrained software prototypes, Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP'95), p.194, June 07-09, 1995
	9	Marleen Add, "Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets" , Ph.D. Diss., KULeuven-ESAT, Oct 1996 (downloadable from http://www.esat.kuleuven.ac.be/acca/reports/phd_marleen.html).
	10	Marleen Add, Rudy Lauwereins, J.A. Peperstraete, "Minimum memory buffers in DSP applications", Electronics Letters, March 17, 1994, Vol. 30, No. 6, pp.469-471.
	11	Marleen Add, Rudy Lauwereins, J. A. Peperstraete, "Buffer Memory Requirements in DSP Applications", Proceedings of the 5th IEEE International Workshop on Rapid System Prototyping, Ed. N. Kanopoulos, IEEE Computer Society Press, Grenoble, France, June 1994, pp. 108-123.
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CITED BY 10

	Marc Geilen , Twan Basten , Sander Stuijk, Minimising buffer requirements of synchronous dataflow graphs with model checking, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Hyunok Oh , Nikil Dutt , Soonhoi Ha, Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphs, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
	Hyunok Oh , Nikil Dutt , Soonhoi Ha, Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Sander Stuijk , Marc Geilen , Twan Basten, Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Chia-Jui Hsu , Suren Ramasubbu , Ming-Yung Ko , José Luis Pino , Shuvra S. Bhattacharyya, Efficient simulation of critical synchronous dataflow graphs, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Ming-Yung Ko , Praveen K. Murthy , Shuvra S. Bhattacharyya, Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls, ACM Transactions on Embedded Computing Systems (TECS), v.6 n.2, p.14-es, May 2007
	Chia-Jui Hsu , Ming-Yung Ko , Shuvra S. Bhattacharyya , Suren Ramasubbu , José Luis Pino, Efficient simulation of critical synchronous dataflow graphs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-28, August 2007
	N. Liveris , H. Zhou , P. Banerjee, A dynamic-programming algorithm for reducing the energy consumption of pipelined system-level streaming applications, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Hyunuk Jung , Hoeseok Yang , Soonhoi Ha, Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis, Journal of Signal Processing Systems, v.52 n.1, p.13-34, July 2008
	Pieter H. Hartel , Theo C. Ruys , Marc C. W. Geilen, Scheduling optimisations for SPIN to minimise buffer requirements in synchronous data flow, Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design, p.1-10, November 17-20, 2008, Portland, Oregon