Calculating worst-case gate delays due to dominant capacitance coupling

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Calculating worst-case gate delays due to dominant capacitance coupling

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 46 - 51

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Florentin Dartu	Carnegie Mellon University, Department of ECE, Pittsburgh, PA
Lawrence T. Pileggi	Carnegie Mellon University, Department of ECE, Pittsburgh, PA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 35, Citation Count: 48

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ABSTRACT

In this paper we develop a gate level model that allows us to determinethe best and worst case delay when there is dominant interconnectcoupling. Assuming that the gate input windows oftransition are known, the model can predict the worst and bestcase noise, as well as the worst and best case impact on delay. Thisis done in terms of a Ceff based gate model under general RCinterconnect loading conditions.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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