Zeros and passivity of Arnoldi-reduced-order models for interconnect networks

ABSTRACT

CAD tools and research in the area of reduced-ordermodeling of large linear interconnect networks have evolvedfrom merely finding a Pad´ e approximation for the givennetwork transfer function to finding an approximate transferfunction that preserves such circuit-theoretic propertiesof the network as stability, passivity, and RLC synthesizability.In particular, preserving passivity guarantees thatthe reduced-order models will be well-behaved when embeddedback in the circuit where the interconnect networkoriginated. While stability can be ascertained by studyingthe poles of the reduced-order transfer function, passivitydepends on both the poles and zeros of the networkdriving-point impedance. In this paper, we present a novelmethod for studying the zeros of reduced-order transferfunctions and show how it yields conclusions about passivityand synthesizability. Moreover, in order to obtain aguaranteed-passive reduced-order model for multiport RCnetworks, a new algorithm based on the Arnoldi iteration ispresented. This algorithm is as computationallyefficient asthe one used to generate guaranteed-stable reduced-ordermodels [Coordinate-transformed Arnoldi for generating guranteed stable reduced-order models for RLC circuits].

REFERENCES

• 1: L. Miguel Silveira , Mattan Kamon , Ibrahim Elfadel , Jacob White, A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.288-294, November 10-14, 1996, San Jose, California, United States
• 2: L. T. Pillage and R. A. Rohrer. Asymptotic Waveform Evaluation for Timing Analysis. IEEE Trans. CAD, 9(4):352-366, April 1990.
• 3: C. L. Ratzlaff and L. T. Pillage. RICE: Rapid interconnect circuit evaluation using AWE. IEEE Trans. CAD, 13(6):763-776, June 1994.
• 4: E. Chiprout and M. S. Nakhla. Analysis of interconnect networks using complex frequency hopping (CFH). IEEE Trans. CAD, 14(2):186-200, February 1995.
• 5: K. Gallivan, E. Grimme, and E Van Dooren. Multi-point Pad6 approximants of large-scale systems via a two-sided rational Krylov algorithm. In 33"d IEEE Conference on Decision and Control, December 1994.
• 6: L. M Silveira, M. Kamon, and J. K. White. Direct computation of reduced-order models for circuit simulation of 3-d interconnect structures. In Proceedings of the 3~d Topical Meeting on Electrical Performance of Electronic Packaging, pages 254-248, Monterey, California, November 1994.
• 7: E Feldmann and R. W. Freund. Efficient linear circuit analysis by Pad6 approximation via the Lanczos process. IEEE Trans. CAD, 14:639-649, May 1995.
• 8: E. A. Guillemin. Synthesis of Passive Networks. John Wiley and Sons, 1957.
• 9: Kevin J. Kerns , Andrew T. Yang, Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations, Proceedings of the 33rd annual conference on Design automation, p.280-285, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240570]
• 10: I. M. Elfadel and David D. Ling. Zeros and passivity of Arnoldireduced-order models for inteconnect networks. Technical report, IBM T.J. Watson Research Center, Yorktown-Heights, NY, 1997.
• 11: R. W. Freund , P. Feldmann, Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.280-287, November 10-14, 1996, San Jose, California, United States
• 12: J. Eric Bracken. Passive modeling of linear interconnect networks. Technical report, ECE, CMU, no date.
• 13: R. A. Horn and C. R. Johnson. Topics in Matrix Theory. Cambridge University Press, 1991.
• 14: Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi, PRIMA: passive reduced-order interconnect macromodeling algorithm, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.58-65, November 09-13, 1997, San Jose, California, United States

INDEX TERMS

Primary Classification:
  J. Computer Applications

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

General Terms:
Algorithms, Design, Measurement, Performance, Theory