| Synthesis of speed-independent circuits from STG-unfolding segment |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 16 - 21
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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A. Semenov
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Department of Computing Science, University of Newcastle, Newcastle upon Tyne, NE1 7RU England
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A. Yakovlev
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Department of Computing Science, University of Newcastle, Newcastle upon Tyne, NE1 7RU England
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E. Pastor
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Department of Computer Architecture, Universitat Politècnica de Catalunya, 08071 Barcelona, Spain
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M. A. Peña
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Department of Computer Architecture, Universitat Politècnica de Catalunya, 08071 Barcelona, Spain
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J. Cortadella
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Department of Computer Architecture, Universitat Politècnica de Catalunya, 08071 Barcelona, Spain
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Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 2
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ABSTRACT
This paper presents a novel technique for synthesis of speed-independentcircuits. It is based on partial order representation ofthe state graph called STG-unfolding segment. The new methoduses approximation technique to speed up the synthesis process.The method is illustrated on the basic implementation architecture.Experimental results demonstrating its efficiency are presented anddiscussed.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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T.A. Chu. Synthesis of Self-Timed VLSI Circuits ~'om Graphtheoretic Specifications. PhD thesis, MIT, 1987.
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Michael Kishinevsky , Alex Kondratyev , Alexander Taubin , Victor Varshavsky , Alex Yakovlev , Eric Napelbaum , Olga Reva, Concurrent hardware: the theory and practice of self-timed design, John Wiley & Sons, Inc., New York, NY, 1994
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A. Semenov and A. Yakovlev. Event-based framework for verification of high-level models of asynchronous circuits. Technical Report 487, University of Newcastle upon Tyne, 1994.
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E.M Sentovich et. al. SIS: A system for sequential circuit synthesis. Memorandum No. UCB/ERL M92/41, University of California, Berkeley, 1992.
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A. Yakovlev. Designing control logic for counterflow pipeline processor using petri nets. Technical Report 522, University of Newcastle upon Tyne, 1995.
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Ch. Ykman-Couvreur, B. Lin, and H. DeMan. ASSASSIN: A synthesis system for asynchronous control circuits. Reference manual, IMEC, 1995.
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