An improved algorithm for minimum-area retiming

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An improved algorithm for minimum-area retiming

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents

Anaheim, California, United States

Pages: 2 - 7

Year of Publication: 1997

ISBN:0-89791-920-3

Authors

Naresh Maheshwari	Department of Electrical & Computer Engineering, Iowa State University, Ames, IA
Sachin S. Sapatnekar	Department of Electrical & Computer Engineering, Iowa State University, Ames, IA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 15

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ABSTRACT

The concept of improving the timing behavior of a circuit by relocatingflip-flops is called retiming and was first presented by Leisersonand Saxe. The ASTRA algorithm proposed an alternativeview of retiming using the equivalence between retiming and clockskew optimization. This work defines the relationship betweenthe Leiserson-Saxe and the ASTRA approaches and utilizes it tosolve the problem of retiming for minimum area. The new algorithm,Minaret, uses the linear programming formulation of theLeiserson-Saxe approach. The underlying philosophy of the ASTRAapproach is incorporated to reduce the number of variablesand constraints in the linear program. This reduction in the sizeof the linear program makes Minaret space and time efficient, enablingminimum area retiming of circuits with over 56,000 gates inunder 15 minutes.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 15

	Naresh Maheshwari , Sachin S. Sapatnekar, Minimum area retiming with equivalent initial states, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.216-219, November 09-13, 1997, San Jose, California, United States
	A. Ranjan , A. Srivastava , V. Karnam , M. Sarrafzadeh, Layout aware retiming, Proceedings of the 11th Great Lakes symposium on VLSI, p.25-30, March 2001, West Lafayette, Indiana, United States
	François R. Boyer , El Mostapha Aboulhamid , Yvon Savaria , Michel Boyer, Optimal design of synchronous circuits using software pipelining techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.4, p.516-532, October 2001
	Klaus Eckl , Jean Christophe Madre , Peter Zepter , Christian Legl, A practical approach to multiple-class retiming, Proceedings of the 36th ACM/IEEE conference on Design automation, p.237-242, June 21-25, 1999, New Orleans, Louisiana, United States
	N. Maheshwari , S. S. Sapatnekar, Efficient minarea retiming of large level-clocked circuits, Proceedings of the conference on Design, automation and test in Europe, p.840-847, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, Marsh: min-area retiming with setup and hold constraints, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.2-6, November 07-11, 1999, San Jose, California, United States
	Karam S. Chatha , Ranga Vemuri, Hardware-Software partitioning and pipelined scheduling of transformative applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.193-208, June 2002
	Abdallah Tabbara , Robert K. Brayton , A. Richard Newton, Retiming for DSM with area-delay trade-offs and delay constraints, Proceedings of the 36th ACM/IEEE conference on Design automation, p.725-730, June 21-25, 1999, New Orleans, Louisiana, United States
	Noureddine Chabini , El Mostapha Aboulhamid , Ismaïl Chabini , Yvon Savaria, Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.187-204, April 2005
	G. Hasteer , A. Mathur , P. Bannerjee, Efficient equivalence checking of multi-phase designs using phase abstraction and retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.3 n.4, p.600-625, Oct. 1998
	Rajeev K. Ranjan , Vigyan Singhal , Fabio Somenzi , Robert K. Brayton, Using combinational verification for sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.32-es, January 1999, Munich, Germany
	Klaus Eckl , Christian Legl, Retiming sequential circuits with multiple register classes, Proceedings of the conference on Design, automation and test in Europe, p.127-es, January 1999, Munich, Germany
	Chao-Yang Yeh , Malgorzata Marek-Sadowska, Minimum-Area Sequential Budgeting for FPGA, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.813, November 09-13, 2003
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003
	Ruibing Lu , Cheng-Kok Koh, Interconnect Planning with Local Area Constrained Retiming, Proceedings of the conference on Design, Automation and Test in Europe, p.10442, March 03-07, 2003