The Mercury Interconnect Architecture: a cost-effective infrastructure for high-performance servers

ABSTRACT

This paper presents HAL's Mercury Interconnect Architecture, an interconnect infrastructure designed to link commodity microprocessors, memory, and I/O components into high-performance multiprocessing servers. Both shared-memory and message-passing systems, as well as hybrid systems are supported by the interconnect. The key attributes of the Mercury Interconnect Architecture are: low latency, high bandwidth, a modular and flexible design, reliability/availability/serviceability (RAS) features, and a simplicity that enables very cost-effective implementations. The first implementation of the architecture links multiple 4-processor Pentium™ Pro based nodes. In a 4-node (16-processor) shared-memory configuration, this system achieves a remote read latency of just over 1 µs, and a maximum interconnect bandwidth of 6.4 GByte/s. Both of these parameters far outpace comparable SCI-based solutions, while utilizing much fewer hardware components.

REFERENCES

• 1: L. Censier and P. Feautrier. A New Solution to Coherence Problems in Multicache Systems. IEEE Transactions on Computers C-27, 12 (December 1978), pages 1112-1118.
• 2: R. Clark and K. Alnes. An SCI Interconnect Chipset and Adapter. In Symposium Record, Hot Interconnects 1V, pages 221-235, August 1996.
• 3: CORPORATE Institute of Electrical and Electronics Engineers, Inc. Staff, IEEE Standard for Scalable Coherent Interface, Science: IEEE Std. 1596-1992, IEEE Standards Office, New York, NY, 1993
• 4: Intel. Pentium~ Pro Family Developer's Manual Volume 3: Operating System Writer's Guide. Intel Corporation, 1996.
• 5: Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
• 6: Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Wolf-Dietrich Weber , Anoop Gupta , John Hennessy , Mark Horowitz , Monica S. Lam, The Stanford Dash Multiprocessor, Computer, v.25 n.3, p.63-79, March 1992 [doi>10.1109/2.121510]
• 7: Daniel E. Lenoski , Wolf-Dietrich Weber, Scalable Shared-Memory Multiprocessing, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1994
• 8: Tom Lovett , Russell Clapp, STiNG: a CC-NUMA computer system for the commercial marketplace, Proceedings of the 23rd annual international symposium on Computer architecture, p.308-317, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 9: T. Lovett and R. Clapp. Private correspondence, February 1997.
• 10: A. Mu, B. Chia, S. Kondapalli, C. Koo, J. Larson, L. Nguyen, R. Sastry, Y. Satsukawa, H.-C. Shih, T. Wicki, C. Wu, K. Yu, and X. Zhang. A 285 MHz 6-port Plesiochronous Router Chip with Non-Blocking Cross-Bar Switch. In 1996 Symposium on VLSI Circuits: Digest of Technical Papers, pages 136-137, 1996.
• 11: Albert Mu , Jeff Larson , Raghu Sastry , Thomas Wicki , Winfried W. Wilcke, A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip, Proceedings of the 41st IEEE International Computer Conference, p.261, February 25-28, 1996
• 12: W.-D. Weber. Scalable Directories for Cache-Coherent Shared-Memory Multiprocessors. Ph.D. Thesis, Stanford University, January 1993. Also available as Stanford University Technical Report CSL-TR-93-557.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  C. Computer Systems Organization

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout

General Terms:
Design, Measurement, Performance, Reliability, Theory