Data caches for superscalar processors

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Data caches for superscalar processors

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International Conference on Supercomputing archive
Proceedings of the 11th international conference on Supercomputing table of contents

Vienna, Austria

Pages: 60 - 67

Year of Publication: 1997

ISBN:0-89791-902-5

Authors

Toni Juan	Dept. Arquitectura de Computadors, Barcelona, Universitat Politecnica de Catalunya, Spain
Juan J. Navarro	Dept. Arquitectura de Computadors, Barcelona, Universitat Politecnica de Catalunya, Spain
Olivier Temam	PRiSM, Versailles University, France

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 32, Citation Count: 14

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 14

	Jude A. Rivers , Gary S. Tyson , Edward S. Davidson , Todd M. Austin, On high-bandwidth data cache design for multi-issue processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.46-56, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	Francisca Quintana , Jesus Corbal , Roger Espasa , Mateo Valero, A cost effective architecture for vectorizable numerical and multimedia applications, Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures, p.103-112, July 2001, Crete Island, Greece
	Jesus Corbal , Roger Espasa , Mateo Valero, Three-dimensional memory vectorization for high bandwidth media memory systems, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Francisca Quintana , Jesus Corbal , Roger Espasa , Mateo Valero, Adding a vector unit to a superscalar processor, Proceedings of the 13th international conference on Supercomputing, p.1-10, June 20-25, 1999, Rhodes, Greece
	Sangyeun Cho , Pen-Chung Yew , Gyungho Lee, A High-Bandwidth Memory Pipeline for Wide Issue Processors, IEEE Transactions on Computers, v.50 n.7, p.709-723, July 2001
	David López , Josep Llosa , Mateo Valero , Eduard Ayguadé, Widening resources: a cost-effective technique for aggressive ILP architectures, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.237-246, November 1998, Dallas, Texas, United States
	Muhamed F. Mudawar, Scalable cache memory design for large-scale SMT architectures, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.65-71, June 20-20, 2004, Munich, Germany
	Bramha Allu , Wei Zhang, Exploiting the replication cache to improve performance for multiple-issue microprocessors, ACM SIGARCH Computer Architecture News, v.33 n.3, June 2005
	David López , Josep Llosa , Mateo Valero , Eduard Ayguadé, Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures, IEEE Transactions on Computers, v.50 n.10, p.1033-1051, October 2001
	Kaveh Jokar Deris , Amirali Baniasadi, Investigating cache energy and latency break-even points in high performance processors, Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, p.13-20, September 16-20, 2006, Seattle, Washington
	B. Allu , W. Zhang , M. Kandala, Exploiting the replication cache to improve cache read bandwidth cost effectively, ACM SIGARCH Computer Architecture News, v.34 n.1, March 2006
	James Tuck , Luis Ceze , Josep Torrellas, Scalable Cache Miss Handling for High Memory-Level Parallelism, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.409-422, December 09-13, 2006
	Kaveh Jokar Deris , Amirali Baniasadi, Investigating cache energy and latency break-even points in high performance processors, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007
	Teemu Pitkänen , Jarno K. Tanskanen , Risto Mäkinen , Jarmo Takala, Parallel Memory Architecture for Application-Specific Instruction-Set Processors, Journal of Signal Processing Systems, v.57 n.1, p.21-32, October 2009