Device and technology optimizations for low power design in deep sub-micron regime

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Device and technology optimizations for low power design in deep sub-micron regime

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 312 - 316

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Kai Chen	211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CA
Chenming Hu	211-72 Cory Hall, E.E.C.S. Department, University of California at Berkeley, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
	2	James D. Meindl, "Low Power Mieroeleetronies: Retrospect and Prospect", Proceedings of the IEEE, pp. 619-63 5, Vol. 83, No. 4, April 1995.
	3	Johannes M. C. Stork, "Technology Leverage for Ultra-Low Power Information Systems", Proceedings of the 1EEE, pp. 607-618, Vol. 83, No. 4, April 1995.
	4	Chenming Hu, Chapter 2 of "Low Power Design Methodologies", edit'ted by Jan M. Rabay and Massoud Pedram, Kluwer Academic Publishers, 1996.
	5	Bijan Davari, Robert H. Dermard, and Ghavam G. Shahidi, "CMOS Scaling for High Performance and Low Power - The Next Ten Years", Proceedings of the 1EEE, pp. 607- 618, Vol. 83, No. 4, April 1995.
	6	Anantha P. Chandrakasan and Robert W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits", Proceedings of 1EEE, pp. 498-523, Vol. 83, No. 4, April 1995.
	7	K. Chen, Chenming Hu, P eng Fang and Ashawant Gupta, "Experimental Confirmation of An Accurate CMOS Gate Delay Model for Gate Oxide and Voltage Scaling", IEEE Electron Device Letters, Vol. 18, No. 6, pp. 275-277, June 1997.
	8	K. Cherg C. H. Warm, J. Duster, P. Ko and C. Hu, "The Impact of Device Sealing and Supply Voltage Change on CMOS Gate Performance", 1EEE Electron Device Letters, pp. 202-204, vol. 17, No. 5, MAY 1996.
	9	K. Chen, H. C. Wann, J. Duster, P. Pramanik, S. Nariani, P. Ko and C. Hu, "'An Accurate Semi-empirical Saturation Drain Current for LDD NMOSFET", IEEE Electron Device Letters, pp. 145-147, vol. 17, No. 3, March 1996.
	10	K. Chen, H.C. Wanrg J. Duster, M. Yoshida, P. Ko and C.' Hu, "MOSFET Carrier Mobility Model Based on Gate Oxide Thickness, Threshold and Gate Voltages", Journal of Solid-State Electronics, pp. 1515-1518, Vol. 39, No. 10, October 1996.
	11	T. Kuroi, et al, 1996 Symposium on VLSI Technology, Japan, pp. 210-211.

Collaborative Colleagues:

Kai Chen: colleagues

Chenming Hu: colleagues

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