Hybrid dual-threshold design techniques for high-performance processors with low-power features

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Hybrid dual-threshold design techniques for high-performance processors with low-power features

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 307 - 311

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Uming Ko	Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas
Andrew Pua	Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas
Anthony Hill	Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas
Pranjal Srivastava	Texas Instruments Incorporated, P.O. Box 660199, M/S 8652, Dallas, Texas

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 13, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S.M. Sze, VLSI TechnoloK~, McGraw-Hill, New York, 1983.
	2	N. Weste et al., Principles of CMOS Design, Addison Wesley, 1993.
	3	A. Chandrakasan et al., IEEE Journal of Solid-State Circuits, vol. 27, 1992.
	4	Uming Ko , Anthony Hill , Poras T. Balsara, Design techniques for high performance, energy efficient control logic, Proceedings of the 1996 international symposium on Low power electronics and design, p.97-100, August 12-14, 1996, Monterey, California, United States
	5	U. Ko et al., "High Performance, Energy Efficient, Master- Slave Flip-Flop Circuits;' Proceedings of the IEEE Symposium on Low Power Electronics, 1995.
	6	L.A. Levet al., "A 64-b Microprocessor with Multimedia Support," IEEE Journal of Solid-State Circuits, vol. 30, no. 11, 1995.

CITED BY 2

	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003

Collaborative Colleagues:

Uming Ko: colleagues

Andrew Pua: colleagues

Anthony Hill: colleagues

Pranjal Srivastava: colleagues

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