Re-mapping for low power under tight timing constraints

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Re-mapping for low power under tight timing constraints

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 287 - 292

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

P. Vuillod	CSL Stanford University
L. Benini	CSL Stanford University
G. De Micheli	CSL Stanford University

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 4

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references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	C. Tsui et al., "Power efficient technology decomposition and mapping under an extended power consumption modcl," IEEE TOAD, vol. 13, n. 9, pp. 1110-1122, 1994.
	3	Sasan Iman , Massoud Pedram, Multi-level network optimization for low power, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.372-377, November 06-10, 1994, San Jose, California, United States
	4	Sasan Iman , Massoud Pedram, Logic extraction and factorization for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.248-253, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217537]
	5	Sasan Iman , Massoud Pedram, POSE: power optimization and synthesis environment, Proceedings of the 33rd annual conference on Design automation, p.21-26, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240522]
	6	Bernhard Rohfleisch , Alfred Kölbl , Bernd Wurth, Reducing power dissipation after technology mapping by structural transformations, Proceedings of the 33rd annual conference on Design automation, p.789-794, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240667]
	7	R. Bahar , M. Burns , G. Hachtel , E. Macii , H. Shin , F. Somenzi, Symbolic computation of logic implications for technology-dependent low-power synthesis, Proceedings of the 1996 international symposium on Low power electronics and design, p.163-168, August 12-14, 1996, Monterey, California, United States
	8	Qi Wang , Sarma B. K. Vrudhula, Multi-level logic optimization for low power using local logic transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.270-277, November 10-14, 1996, San Jose, California, United States
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	11	L. Benini et al., "Generalized matchingt a new approach to concurrent logic optimization and library binding/' A aM TODAES, 1997.
	12	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	13	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	14	R. Iris Bahar , Erica A. Frohm , Charles M. Gaona , Gary D. Hachtel , Enrico Macii , Abelardo Pardo , Fabio Somenzi, Algebraic decision diagrams and their applications, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.188-191, November 07-11, 1993, Santa Clara, California, United States
	15	P. Vuillod et al., "Generalized matching from theory to practice," in preparation.
	16	Y. Watanabe et al., "Permissible functions for multloutput components in combinational logic optimizatlont" IEEE TOAD vol. 15, no. 7, pp. 734-744, 1996.
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CITED BY 4

	R. Iris Bahar , Ernest T. Lampe , Enrico Macii, Power optimization of technology-dependent circuits based on symbolic computation of logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.3, p.267-293, July 2000
	Balakrishna Kumthekar , Luca Benini , Enrico Macii , Fabio Somenzi, In-place power optimization for LUT-based FPGAs, Proceedings of the 35th annual conference on Design automation, p.718-721, June 15-19, 1998, San Francisco, California, United States
	Tony Givargis , Frank Vahid, Interface exploration for reduced power in core-based systems, Proceedings of the 11th international symposium on System synthesis, p.117-122, December 02-04, 1998, Hsinchu, Taiwan, China
	Patrick Vuillod , Luca Benini , Giovanni De Micheli, Generalized matching from theory to application, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.13-20, November 09-13, 1997, San Jose, California, United States

Collaborative Colleagues:

P. Vuillod: colleagues

L. Benini: colleagues

G. De Micheli: colleagues

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