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An object code compression approach to embedded processors
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 265 - 268  
Year of Publication: 1997
ISBN:0-89791-903-3
Authors
Yukihiro Yoshida  Dept. Information Systems Engineering, Osaka University
Bao-Yu Song  Dept. Information Systems Engineering, Osaka University
Hiroyuki Okuhata  Dept. Information Systems Engineering, Osaka University
Takao Onoye  Dept. Information Systems Engineering, Osaka University
Isao Shirakawa  Dept. Information Systems Engineering, Osaka University
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 30,   Citation Count: 24
Additional Information:

references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Y. Otaguro: "Design of a low-power RISC processor for embedded applications", Technical Report of IEICE, ICD95-60, Jun. 1995 (in Japanese).
 
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T. Enomoto: "Low-power CMOS and GaAs digital design for inultimedia LSIs", Technical Report of IEIGE, ICD95-69, Aug. 1995 (in Japanese).
 
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S. Horiguchi, T. Tsukahara, and H. Fukuda: "Lowpower LSI circuit technologies for portable terminal equipment", IEICE Trans. Electronics, vol. E78-C, no. 12, pp. 1655-1667, Dec. 1995.
 
7
S. Shigematsu, S. Mutoh, and Y. Maistjya: "Power management technique for I-V LSIs using embeflth,cl processor", in Proc. tEEE Custom Intt:!iluted (Ji~vuil,,i Conference, pp. 111-114, May 1996.
 
8
G. C. Cardarilli, M. Salmeri, A. Salsano, att~l O. Simonelli: "Bus architecture for low-power VLSI cligilal circuit.s", in Proc. IEEE lnt'l Syrup. Oirc.uils and Sys. terns, pp. 4.21-4.24, May 1996.
 
9
S. Iwata, T. Shimizu, J. Korematu, K. Dosaka~ I{. Tsubota, and K. Saitoh: "Porformance (;valtlati(~u o{' a-microprocessor with on-chip DRAM arid lligll Inuz~lwidth internal bus", in Proc. IEEE Custom Inlcgralcd Circuits Conference, pp. 269-272, May 1996.
 
10
T. Sllimizu, J. Korematu, M. Satotl, H. Ko,ul~), S. Iwata, K. Sawai, N. Okl,mura, K. lshimi, Y. Nakanl~l~), M. Kuman()ya, K. Dosaka, A. Yalnazaki, Y, A.jic~ka, l l. Tsubota, Y. Nonomura, T. Urabe, J. Hinata, at~(i l(. Saitoll: "A multimedia 32b RJSC microl)ro('(,ssc)r wil ii 16Ml) DRAM", in IEEE ISSGC Digest of Technical i~a. pets, FP13.4, Feb. 1996.
 
11
Y. Yamagata, T. Ishibashi, Y. Sano, Y. K()ga, M. Yoshida, and A. Sugo: "32-I)it R.IS(~ nlicrocolll,n)ll(,r V853", NEC Technical Journal, w)l. d9, no,3, {31). 55 60, Apr. 1996.
 
12

CITED BY  24
Collaborative Colleagues:
Yukihiro Yoshida: colleagues
Bao-Yu Song: colleagues
Hiroyuki Okuhata: colleagues
Takao Onoye: colleagues
Isao Shirakawa: colleagues