A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications

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A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 220 - 224

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Hyung-Joon Kwon	Korea Advanced Institute of Science and Technology
Kwyro Lee	Korea Advanced Institute of Science and Technology

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Richard E. Blahut, Theory and Practice oJ ~rmr Control Codes. Addison-Wesley, 1984.
	2	Gadiel Seroussi, "A Systolic Reed-Solomon Encoder," IEEE trans. Inform. Theory, vol.37, no, 6, pp. 1217-1220, July. 1991.
	3	A.P. Chandrakasen., et al., "Low-power Chipset for Portable Multimedia Applications," in the proceedings of the '94 IEEE International Solid State Circuits Conference, Feb. 1994
	4	Menahem Lowy, "Low power spread spectrum code generator based on parallel shift register implementation," in proceeding of the '94 IEEE Symposium on Low Power Electronics., pp. 22-23, Aug. 1994.
	5	Osamu K., et al, "A High Speed Signal Processing for Quadruple Speed CD-ROM," IEEE trans. Consumer Electronics, vol. 40, no. 3, pp679-685, Aug. 1994.

Collaborative Colleagues:

Hyung-Joon Kwon: colleagues

Kwyro Lee: colleagues

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