Minimizing energy dissipation in high-speed multipliers

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Minimizing energy dissipation in high-speed multipliers

Full text

Pdf (634 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 214 - 219

Year of Publication: 1997

ISBN:0-89791-903-3

Author

Rafael Fried

Swiss Federal Institute of Technology (EPFL), Electronics Laboratory, ELB-Ecublens, CH-1015 Lausanne, Switzerland

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 23, Citation Count: 7

Additional Information:

references cited by collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/263272.263337 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A.bdellatif Bellaouar , Mohamed I. Elmasry , Jonathan Allen, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, Norwell, MA, 1995
	2	K. Yano et al., "A 3.8 nS CMOS 16 x 16-b Multiplier Using Complementary Pass-Transistor Logic", IEEE JSSC, Vol. 25, No. 2, pp. 388-395, Apr. 1990.
	3	J. Mori aL, "A 10 nS 54 x 54-b CMOS Parallel Structured Full Array Multiplier with 0.5-~m CMos Technology", IEEE JSSC, Vol. 26, No. 4, pp. 600- 605, Apr. 1991.
	4	N. Ohkubo et al., "A 4.4 nS CMOS 54 x 54-b Multiplier Using Pass-Transistor Multiplexer", IEEE JSSC, Vol. 30, No. 3, pp. 251-257, Mar. 1995.
	5	G. Goto et al., "A 54 x 54-b Regularly Structured Tree Multiplier", IEEE JSSC, Vol. 27, No. 9, pp. 1229- 1235, Sept. 1992.
	6	P.J. Song and G. De Micheli, "Circuit and Architecture Trade-offs for High-Speed Multiplication", IEEE JSSC, Vol. 26, No. 9, pp. 1184-1198, Sept. 1991.
	7	Marco Annaratone, Digital CMOS circuit design, Kluwer Academic Publishers, Norwell, MA, 1986
	8	Hans Lindkvist , Per Anderson, Techniques for Fast CMOS-based Conditional Sum Adders, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.626-635, October 10-12, 1994
	9	T.K. Callaway and E. E. Swartzlander Jr., "Estimating the Power consumption of CMOS Adders", 1 lth Symp. on Comp. Arithmetic, pp. 210-219, June 1993.
	10	M. Suzuki et al., "A 1.5 nS CMOS ALU in Double Pass-Transistor Logic", IEEE JSSC, Vo}. 28, No. 11, pp. 1145-1151, Nov. 1993.
	11	A. Inoue et al., "A 4. lnS Compact 54x54b Multiplier Utilizing Sign Select Booth encoders", ISSCC'97 pp. 416-417.

CITED BY 7

	Bryan Ackland , Chris Nicol, High performance DSPs - what's hot and what's not?, Proceedings of the 1998 international symposium on Low power electronics and design, p.1-6, August 10-12, 1998, Monterey, California, United States
	Hoon Jae Ki , Yun Seob Song , Woo Hyun Paik , Sang Won Lee , Chul Hee Kang , Soo Won Kim, A Low Power Adaptive Equalizer for PRML Disk-Drive Read Channels, Analog Integrated Circuits and Signal Processing, v.34 n.3, p.211-220, March 2003
	Yijun Liu , Steve Furber, The design of a low power asynchronous multiplier, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Wen-Chang Yeh , Chein-Wei Jen, High-Speed Booth Encoded Parallel Multiplier Design, IEEE Transactions on Computers, v.49 n.7, p.692-701, July 2000
	Abdoul Rjoub , Odysseas Koufopavlou, Multithreshold voltage low-swing/low-voltage techniques in logic gates, Integration, the VLSI Journal, v.38 n.2, p.283-298, December 2004
	Hwang-Cherng Chow , I-Chyn Wey, High speed pipelined Booth multiplier for DSP applications, Proceedings of the 9th International Conference on Circuits, p.1-6, July 11-13, 2005, Athens, Greece
	Shuli Gao , Dhamin Al-Khalili , Noureddine Chabini, Efficient scheme for implementing large size signed multipliers using multigranular embedded DSP blocks in FPGAs, International Journal of Reconfigurable Computing, 2009, p.1-11, January 2009

Collaborative Colleagues:

Rafael Fried: colleagues

Adobe Acrobat

QuickTime

Windows Media Player

Real Player