An extended addressing mode for low power

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An extended addressing mode for low power

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 208 - 213

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Atul Kalambur	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA
Mary Jane Irwin	Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 6

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Huzefa Mehta, Robert Owens, and Mary Jane Irwin. "Instruction Level Power Profiling" International Conference on Acoustics, Speech and Signal Processing, 1996.
	2	Huzefa Abdulhusain Mehta , Mary Jane Irwin , Robert Michael Owens, System level power analysis, 1996
	3	J. Bunda , D. Fussell , W. C. Athas, Energy-efficient instruction set architecture for CMOS microprocessors, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.298, January 04-07, 1995
	4	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
	5	Larry B. Hostetler and Brian Mirtich. "DLXsim : A Simulator for DLX"
	6	Liam Goudge , Simon Segars, Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and Consumer Applications, Proceedings of the 41st IEEE International Computer Conference, p.176, February 25-28, 1996
	7	Ashley Saulsbury , Fong Pong , Andreas Nowatzyk, Missing the memory wall: the case for processor/memory integration, Proceedings of the 23rd annual international symposium on Computer architecture, p.90-101, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	8	David Patterson, Thomas Anderson and Katherine Yelick. "Intelligent DRAM (/RAM):' http://iran~cs.berkeley.edg
	9	Dan Dobberpuhl, The design of a high performance low power microprocessor, Proceedings of the 1996 international symposium on Low power electronics and design, p.11-16, August 12-14, 1996, Monterey, California, United States
	10	A. Salz , M. Horowitz, IRSIM: an incremental MOS switch-level simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.173-178, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74412]

CITED BY 6

	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Susan Cotterell , Frank Vahid, Synthesis of customized loop caches for core-based embedded systems, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.655-662, November 10-14, 2002, San Jose, California
	Nikolaos Bellas Ibrahim Hajj , George Stamoulis , N. Bellas , C. Polychronopoulos, Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors, Proceedings of the 1998 international symposium on Low power electronics and design, p.70-75, August 10-12, 1998, Monterey, California, United States
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	Sanghyun Park , Aviral Shrivastava , Nikil Dutt , Alex Nicolau , Yunheung Paek , Eugene Earlie, Bypass aware instruction scheduling for register file power reduction, ACM SIGPLAN Notices, v.41 n.7, July 2006
	Wu-An Kuo , TingTing Hwang , Allen C. -H. Wu, Decomposition of Instruction Decoder for Low Power Design, Proceedings of the conference on Design, automation and test in Europe, p.10664, February 16-20, 2004

Collaborative Colleagues:

Atul Kalambur: colleagues

Mary Jane Irwin: colleagues

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