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K2: an estimator for peak sustainable power of VLSI circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 178 - 183

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Michael S. Hsiao	Department of Electrical and Computer Engineering, Rutgers University, Piscataway, NJ
Elizabeth M. Rudnick	Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL
Janak H. Patel	Center for Reliable and High-Performance Computing, University of Illinois, Urbana, IL

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 8

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
	4	Tan-Li Chou , Kaushik Roy, Statistical estimation of sequential circuit activity, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.34-37, November 05-09, 1995, San Jose, California, United States
	5	Tan-Li Chou , Kaushik Roy, Accurate power estimation of CMOS sequential circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.3, p.369-380, Sept. 1996 [doi>10.1109/92.532037]
	6	Chi-Ying Tsui , José Monteiro , Massoud Pedram , Srinivas Devadas , Alvin M. Despain , Bill Lin, Power estimation methods for sequential logic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.3, p.404-416, Sept. 1995 [doi>10.1109/92.406998]
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CITED BY 8

	Yi-Min Jiang , Kwang-Ting Cheng , An-Chang Deng, Estimation of maximum power supply noise for deep sub-micron designs, Proceedings of the 1998 international symposium on Low power electronics and design, p.233-238, August 10-12, 1998, Monterey, California, United States
	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Effects of delay models on peak power estimation of VLSI sequential circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.45-51, November 09-13, 1997, San Jose, California, United States
	Rajat Chaudhry , David Blaauw , Rajendran Panda , Tim Edwards, Current signature compression for IR-drop analysis, Proceedings of the 37th conference on Design automation, p.162-167, June 05-09, 2000, Los Angeles, California, United States
	Qinru Qiu , Qing Wu , Massoud Pedram, Maximum power estimation using the limiting distributions of extreme order statistics, Proceedings of the 35th annual conference on Design automation, p.684-689, June 15-19, 1998, San Francisco, California, United States
	Yi-Min Jiang , Tak K. Young , Kwang-Ting Cheng, VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs, Proceedings of the 1999 international symposium on Low power electronics and design, p.156-161, August 16-17, 1999, San Diego, California, United States
	D. T. Blaauw , A. Dharchoudhury , R. Panda , S. Sirichotiyakul , C. Oh , T. Edwards, Emerging power management tools for processor design, Proceedings of the 1998 international symposium on Low power electronics and design, p.143-148, August 10-12, 1998, Monterey, California, United States
	Cheng-Tao Hsieh , Jian-Cheng Lin , Shih-Chieh Chang, A vectorless estimation of maximum instantaneous current for sequential circuits, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.537-540, November 07-11, 2004
	Michael S. Hsiao, Peak power estimation using genetic spot optimization for large VLSI circuits, Proceedings of the conference on Design, automation and test in Europe, p.38-es, January 1999, Munich, Germany

Collaborative Colleagues:

Michael S. Hsiao: colleagues

Elizabeth M. Rudnick: colleagues

Janak H. Patel: colleagues

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