Low power motion estimation design using adaptive pixel truncation

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Low power motion estimation design using adaptive pixel truncation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 167 - 172

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Zhong-Li He	Dept. of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
Kai-Keung Chan	Dept. of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
Chi-Ying Tsui	Dept. of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong
Ming L. Liou	Dept. of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 20, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K.K. Chan and C.Y. Tsui. Exploring the power consumption of different motion estimation architectures for video compression. Proceedings of IEEE ISGAS'97, June 1997.
	2	K. M. Yang et al. A family of vlsi designs for the motion compensation block-matching algorithm. IEEE Trans. on Circuits and Systems, 36(10):1317-1325, Oct. 1989.
	3	Masayuld Mizuno el. al. A 1.5w single-chip MPEG MP@ML encoder with low-power motion estimation and clocking. Proceedings of IEEE ISSCC, pages 256--257, Feb. 1997.
	4	Q. Wu et al. Statistical design of macro-models for rtlevel power estimation. Proceedings of ASP-DAC, pages 523-528, Feb. 1997.
	5	Karl Guttag , Robert J. Gove , Jerry R. Van Aken, A Single-Chip Multiprocessor for Multimedia: the MVP, IEEE Computer Graphics and Applications, v.12 n.6, p.53-64, November 1992 [doi>10.1109/38.163625]
	6	Zhong L. He and Ming L. Lion. Reducing hardware complexity of motion estimation algorithms using truncated pixels. Proceedings of IEEE ISCAS'97, June 1997.
	7	P. Landman J. Rabaey. Power estimation for high level synthesis. Proceedings Thv European Conference on Design Automation, pages 361-6, 1993.
	8	N. Demassieux P. Pirsch and W. Gehrke. Vlsi architectures for video compression---a survey. Proceedings of IEEE, (2):220-246, Feb. 1995.
	9	Telenor R&D. H.263 simulator based on the thinS. Technical report, 1996.

CITED BY 2

	Vasily G. Moshnyaga , Koji Inoue , Mizuka Fukagawa, Reducing energy consumption of video memory by bit-width compression, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Vasily G. Moshnyaga, Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits, Journal of VLSI Signal Processing Systems, v.33 n.1, p.75-8, January-February 2003

Collaborative Colleagues:

Zhong-Li He: colleagues

Kai-Keung Chan: colleagues

Chi-Ying Tsui: colleagues

Ming L. Liou: colleagues

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