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Analytical energy dissipation models for low-power caches
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 143 - 148  
Year of Publication: 1997
ISBN:0-89791-903-3
Authors
Milind B. Kamble  Department of Computer Science, State University of New York, Binghamton, NY
Kanad Ghose  Department of Computer Science, State University of New York, Binghamton, NY
Sponsors
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 11,   Downloads (12 Months): 34,   Citation Count: 100
Additional Information:

references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
ERB+ 95
 
Intel 96
Intel Corporation, Pentium-Pro data book, 1996.
 
JBD+ 93
3"ouppi, N., et al., "A 300-MHz 115-W 32-b Bipolar ECL Microprocessor", in IEEE Journal of Solid-State Circuits, Nov. 1993, pp. 1152-1165.
 
KaGh 97
 
Larus 96
Larus, J., "SHM: A MIPS 2000 Simulator", available form Univ. W'm., CS ftp si~.
 
Mon 96
Montanaro, J. et al., "A 160 MHz, 32b 0.5 W CMOS RISC Microprocessor", in IEEE ISSCC 1996 Digest of Papors, 1996.
 
Ro 96
Rogers, A., "CL-.SPIM: A Cycle Level Simulator for the MIPS 2000", available form Univ. Wis., CS ftp site,
Smith 82
 
StBu 95
SuDe 95
 
WeEs 93
 
Wijo 94
Wilton, S. E., and 3"ouppi, N.,"An Enhanced Access and Cycle Time Model for On-Chip Caches", DEC WRL Research Report 93/5, July 1994

CITED BY  100
Collaborative Colleagues:
Milind B. Kamble: colleagues
Kanad Ghose: colleagues