Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

Full text

Pdf (727 KB)

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 137 - 142

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

R. S. Bajwa	Semiconductor Research Laboratory, R&D Division, Hitachi America, Ltd.
N. Schumann	Semiconductor Research Laboratory, R&D Division, Hitachi America, Ltd.
H. Kojima	Semiconductor Research Laboratory, R&D Division, Hitachi America, Ltd.

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/263272.263309 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
	2	H. Kojima, D. Gomy, K. Nitta, and K. Sasaki. Power Analysis of a Programmable DSP for Architecture/Program Optimization. In IEEE Symposium on Low Power Electronics, Digest of Tech. Papers, pages 26-27, Oct. 1995.
	3	Dan Dobberpuhl, The design of a high performance low power microprocessor, Proceedings of the 1996 international symposium on Low power electronics and design, p.11-16, August 12-14, 1996, Monterey, California, United States
	4	G. Gerosa, S. Gary, C. Dietz, D. Pham, K. Hoover, J. Alvarez, H. Sanehez, P. Ippolito, T. Ngo, S. Liteh, J, Eno, J, Golab, N. Vandersehaaf, and J. Kahle. A 2.2 W, 80 MHz Supersealar RISC Microprocessor. IEEE Journal of Solid State C#r.ults, 29(12):1440-1454, Dee. 1994.
	5	M. Favalli , L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proceedings of the 1995 international symposium on Low power design, p.123-128, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224103]
	6	M. Favalli , L. Benini, Analysis of glitch power dissipation in CMOS ICs, Proceedings of the 1995 international symposium on Low power design, p.123-128, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224103]
	7	M. Hiraki , R. Bajwa , H. Kojima , D. Gorny , K. Nitta , A. Shridhar , K. Sasaki , K. Seki, Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer, Proceedings of the 1996 international symposium on Low power electronics and design, p.353-358, August 12-14, 1996, Monterey, California, United States

CITED BY 2

	Rita Yu Chen , Mary Jane Irwin , Raminder S. Bajwa, Architecture-level power estimation and design experiments, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.1, p.50-66, Jan. 2001
	Rita Yu Chen , Robert M. Owens , Mary Jane Irwin , R. S. Bajwa , Raminder S. Bajwa, Validation of an architectural level power analysis technique, Proceedings of the 35th annual conference on Design automation, p.242-245, June 15-19, 1998, San Francisco, California, United States

Collaborative Colleagues:

R. S. Bajwa: colleagues

N. Schumann: colleagues

H. Kojima: colleagues

Adobe Acrobat

QuickTime

Windows Media Player

Real Player