Cycle-accurate macro-models for RT-level power analysis

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Cycle-accurate macro-models for RT-level power analysis

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 125 - 130

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Qinru Qiu	Department of Electrical Engineering-Systems, University of Southern California
Qing Wu	Department of Electrical Engineering-Systems, University of Southern California
Massoud Pedram	Department of Electrical Engineering-Systems, University of Southern California
Chih-Shun Ding	Rockwell Semiconductor Systems, Newport Beach Division

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 10

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Powell and P. Chau, "Esitmating power dissipation of VLSI signal processing chips: The PFA techniques", Proceeedings of IEEE Workshop on VLSI Signal Processing IV, vol. IV, pp.250-259, 1990.
	2	P.Landman and J. Rabaey, "Power esitmation for high-level synthesis", Proceedings of IEEE European Design Automation Conference, pp.361-366, Feb, 1993,
	3	D. Liu and C. Svensoon, "Power consumption estimation in CMOS VLSI chips", IEEE Journal of Solid State Circuits, vol. 29, pp.663-670, Jun. 1994.
	4	Paul E. Landman , Jan M. Rabaey, Activity-sensitive architectural power analysis for the control path, Proceedings of the 1995 international symposium on Low power design, p.93-98, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224098]
	5	Q. Wu, C. Ding, C. Hsieh, and M. Pedram, "Statistical Design of Macro-models For RT-Level Power Evaluation", Proceedings of the Asia and South Pacific Design Automation Conference, pp.523-528, Jan. 1997.
	6	J. Neter, W. Wasseman, and M. H. Kutner, Applied Linear Regrssion Models, Second Edition, Richard D, Irwin, Ine, 1989.
	7	PowerMill User manual, Release 3.1, EPIC Design Technology, 1994

CITED BY 10

	A. Bogliolo , L. Benini , G. De Micheli, Characterization-free behavioral power modeling, Proceedings of the conference on Design, automation and test in Europe, p.767-773, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Alessandro Bogliolo , Luca Benini, Node sampling: a robust RTL power modeling approach, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.461-467, November 08-12, 1998, San Jose, California, United States
	Radu Marculescu , Diana Marculescu , Massoud Pedram, Non-stationary effects in trace-driven power analysis, Proceedings of the 1999 international symposium on Low power electronics and design, p.133-138, August 16-17, 1999, San Diego, California, United States
	Zhanping Chen , Kaushik Roy , Edwin K. P. Chong, Estimation of power sensitivity in sequential circuits with power macromodeling application, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.468-472, November 08-12, 1998, San Jose, California, United States
	A. Bona , M. Sami , D. Sciuto , V. Zaccaria , C. Silvano , R. Zafalon, Energy estimation and optimization of embedded VLIW processors based on instruction clustering, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Zhanping Chen , Kaushik Roy, A power macromodeling technique based on power sensitivity, Proceedings of the 35th annual conference on Design automation, p.678-683, June 15-19, 1998, San Francisco, California, United States
	Alessandro Bogliolo , Roberto Corgnati , Enrico Macii , Massimo Poncino, Parameterized RTL power models for combinational soft macros, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.284-288, November 07-11, 1999, San Jose, California, United States
	J. Haid , G. Kaefer , Ch. Steger , R. Weiss, Run-time energy estimation in system-on-a-chip designs, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Alessandro Bolgiolo , Roberto Corgnati , Enrico Macii , Massimo Poncino, Parameterized RTL power models for soft macros, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.880-887, 12/1/2001
	Prashant Agrawal , Srinivasa R. STG , Ajit N. Oke , Saurabh Vijay, A path based modeling approach for dynamic power estimation, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy

Collaborative Colleagues:

Qinru Qiu: colleagues

Qing Wu: colleagues

Massoud Pedram: colleagues

Chih-Shun Ding: colleagues

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