Enhanced prediction of energy losses during adiabatic charging

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Enhanced prediction of energy losses during adiabatic charging

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 104 - 107

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

A. Schlaffer	Institute for Network Theory and Circuit Design, Technical University of Munich, Arcisstr. 21, D-80290 Munich
J. A. Nossek	Institute for Network Theory and Circuit Design, Technical University of Munich, Arcisstr. 21, D-80290 Munich

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	William C. Athas , Lars J. Svensson , Jeffrey G. Koller , Nestoras Tzartzanis , Eric Ying-Chin Chou, Low-power digital systems based on adiabatic-switching principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.398-407, Dec. 1994 [doi>10.1109/92.335009]
	2	David J. Frank , Paul M. Solomon, Electroid-oriented adiabatic switching circuits, Proceedings of the 1995 international symposium on Low power design, p.197-202, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224116]
	3	Y. Moon and D.-K. Jeong. An efficient charge recovery logic circuit. IEEE Journal of Solid-Sta~e Circuits, 31:514-522, April 1996.
	4	A. Schlatfer. An adiabatic full-adder using passtransistors and precharging. Technical Report TI_VM-LNS-TR-96-6, Technical University Munich, October 1996.
	5	John P. Uyemura, Fundamentals of MOS digital integrated circuits, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1988
	6	Y. Ye and K. Roy. Energy recovery circuits using reversible and partially reversible logic. IEEE Transactions on Circuits and Systems, 43:769-778, September 1996.

Collaborative Colleagues:

A. Schlaffer: colleagues

J. A. Nossek: colleagues

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