Quasi-static energy recovery logic and supply-clock generation circuits

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Quasi-static energy recovery logic and supply-clock generation circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 96 - 99

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Yibin Ye	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Kaushik Roy	School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Georgios I. Stamoulis	Low Power Design Technology, Intel Corp., Santa Clara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 14, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	William C. Athas , Lars J. Svensson , Jeffrey G. Koller , Nestoras Tzartzanis , Eric Ying-Chin Chou, Low-power digital systems based on adiabatic-switching principles, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.398-407, Dec. 1994 [doi>10.1109/92.335009]
	2	W.C.Athas, L."J'.Svensson and N.Tzartzanis, "A Resonant Signal Driver for Two-Phase, Almost-Non-Overlapping Clocks," ISCAS.96.
	3	l.S.Denker, S.C.Avery, A.G.Dickinson, A.Kramer, and T.R.Wik, "Adiabatic Computing with the 2N-2N2D logic Family," in Proc. Int. Workshop on Low Power Design, Napa Valley, California, 1994, pp. 183-187.
	4	S.G.Younis and T.F.Knight, "Asymptotically Zero Energy Split- Level Charge Recovery Logic," in Proc. Int. Workshop on Low Power Design, Napa Valley, California, 1994, pp. 177-182.
	5	A.G. Dickinson and J.S.Denker, "Adiabatic Dynamic Logic," IEEE Journal of Solid.State Circuits, Vol.30, No.3, March 1995, pp.311-315.
	6	Y. Ye and K. Roy, "Energy Recovery Circuits Using Reversible and Partially Reversible Logic," IEEE Trans. on Circuits and Systems I, September 1996, pp. 969-779.
	7	D. Somasekhar, Y. Ye, and K. Roy, "An Energy Recovery Static RAM Memory Core," IEEE Symposium on Low Power Elec. tronics, San Jose, October 1995.
	8	M.C.Knapp, P.J.Kindlmann and M.C.Papaefthymiou, "Implementing and Evaluating Adiabatic Arithmetic Units," IEEE Custom Integrated Circuits Conference, San Diego, California, 1996, pp. i15-I18.
	9	V.De and J.D.Meindl, "Complementary Adiabatic MOS Logic Families for Gigascale Integration," Digest of Technical Papers, ISSCC, 1996, pp. 298-299.

CITED BY 2

	Hendrawan Soeleman , Kaushik Roy, Digital CMOS logic operation in the sub-threshold region, Proceedings of the 10th Great Lakes symposium on VLSI, p.107-112, March 02-04, 2000, Chicago, Illinois, United States
	Hendrawan Soeleman , Kaushik Roy, Ultra-low power digital subthreshold logic circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.94-96, August 16-17, 1999, San Diego, California, United States

Collaborative Colleagues:

Yibin Ye: colleagues

Kaushik Roy: colleagues

Georgios I. Stamoulis: colleagues

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