Scheduling for power reduction in a real-time system

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Scheduling for power reduction in a real-time system

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 84 - 87

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Jason J. Brown	Hewlett-Packard Laboratories, Bristol, UK
Danny Z. Chen	Dept. of Computer Science & Engineering, Univ. of Notre Dame, Notre Dame, IN
Garrison W. Greenwood	Dept. of Electrical & Computer Engineering, Western Michigan Univ., Kalamazoo, MI
Xiaobo Hu	Dept. of Computer Science & Engineering, Univ. of Notre Dame, Notre Dame, IN
Richard W. Taylor	Hewlett-Packard Laboratories, Bristol, UK

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 14, Citation Count: 7

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mazhar Alidina , José Monteiro , Srinivas Devadas , Abhijit Ghosh , Marios Papaefthymiou, Precomputation-based sequential logic optimization for low power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.426-436, Dec. 1994 [doi>10.1109/92.335011]
	2	A.bdellatif Bellaouar , Mohamed I. Elmasry , Jonathan Allen, Low-Power Digital VLSI Design Circuits and Systems, Kluwer Academic Publishers, Norwell, MA, 1995
	3	X. Hu, S. Bass and R. Harber, "Minimizing the number of delay buffers in the synchronization of pipelined systems", IEEE Trans. on CAD of Integ. Cir. ft Sys, 13(12), 1441-1449, 1994
	4	Xiabo (Sharon) Hu , Garrison W. Greenwood , Joseph G. D'Ambrosio, An Evolutionary Approach to Hardware/ Software Partitioning, Proceedings of the 4th International Conference on Parallel Problem Solving from Nature, p.900-909, September 22-26, 1996
	5	Kumar N. Lalgudi , Marios C. Papaefthymiou , Miodrag Potkonjak, Optimizing systems for effective block-processing: the k-delay problem, Proceedings of the 33rd annual conference on Design automation, p.714-719, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240653]
	6	C. Leiserson and J. Saxe, "Retiming synchronous circuitry', Algorithmiea, 6(1), 5-35, 1991
	7	José Monteiro , Srinivas Devadas , Pranav Ashar , Ashutosh Mauskar, Scheduling techniques to enable power management, Proceedings of the 33rd annual conference on Design automation, p.349-352, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240584]
	8	M. Potkonjak and J. Rabaey, "Pipelining: just another transformation", Int'l Conf. on Application Specific Array Processors, 163-175, 1992
	9	Massoud Pedram , Jan M. Rabaey, Power Aware Design Methodologies, Kluwer Academic Publishers, Norwell, MA, 2002
	10	Vivek Tiwari , Sharad Malik , Pranav Ashar, Guarded evaluation: pushing power management to logic synthesis/design, Proceedings of the 1995 international symposium on Low power design, p.221-226, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224120]

CITED BY 7

	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli, Power-aware operating systems for interactive systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.119-134, April 2002
	Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli, Low-power task scheduling for multiple devices, Proceedings of the eighth international workshop on Hardware/software codesign, p.39-43, May 2000, San Diego, California, United States
	Yung-Hsiang Lu , Luca Benini , Giovanni De Micheli, Requester-aware power reduction, Proceedings of the 13th international symposium on System synthesis, September 20-22, 2000, Madrid, Spain
	Niraj K. Jha, Low power system scheduling and synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Suet-Fei Li , Roy Sutton , Jan Rabaey, Low power operating system for heterogeneous wireless communication system, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000

Collaborative Colleagues:

Jason J. Brown: colleagues

Danny Z. Chen: colleagues

Garrison W. Greenwood: colleagues

Xiaobo Hu: colleagues

Richard W. Taylor: colleagues

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