Low power high level synthesis by increasing data correlation

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Low power high level synthesis by increasing data correlation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1997 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 62 - 67

Year of Publication: 1997

ISBN:0-89791-903-3

Authors

Dongwan Shin	School of Electrical Engineering, Seoul 151-742, Korea
Kiyoung Choi	School of Electrical Engineering, Seoul 151-742, Korea

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 2

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
	2	Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
	3	A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Low-power CMOS digitial design," 1EEE J. of Solid- State Circuits, pp. 473-484, 1992.
	4	A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W. Brodersen, "Opftmizing power using transformation," 1EEE Tr. on CAD/ICAS, pp. 12- 31, Jan. 1995.
	5	Laurence Goodby , Alex Orailoglu , Paul M. Chau, Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.323-326, October 10-12, 1994
	6	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	7	E. Musoll , J. Cortadella, Scheduling and resource binding for low power, Proceedings of the 8th international symposium on System synthesis, p.104-109, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224523]
	8	Renu Mehra , Lisa M. Guerra , Jan M. Rabaey, Low-power architectural synthesis and the impact of exploiting locality, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.239-258, Aug./Sept. 1996 [doi>10.1007/BF01130408]
	9	Mani B. Srivastava , Anantha P. Chandrakasan , R. W. Brodersen, Predictive system shutdown and other architectural techniques for energy efficient programmable computation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.1, p.42-55, March 1996 [doi>10.1109/92.486080]
	10	A. Abnous and L M. Rabaey, "Ultra-low-power domain-specific multimedia processors,' in Prec. of 1EEE VLSI Signal Processing Workshop, Oct. 1996.
	11	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	12	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]

CITED BY 2

	Junghwan Choi , Jinhwan Jeon , Kiyoung Choi, Power minimization of functional units partially guarded computation, Proceedings of the 2000 international symposium on Low power electronics and design, p.131-136, July 25-27, 2000, Rapallo, Italy
	C. Gebotys , R. Gebotys , S. Wiratunga, Power minimization derived from architectural-usage of VLIW processors, Proceedings of the 37th conference on Design automation, p.308-311, June 05-09, 2000, Los Angeles, California, United States

Collaborative Colleagues:

Dongwan Shin: colleagues

Kiyoung Choi: colleagues

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